@User I have a question regarding openram. I have attached two snaps of 1kb openram(sram) simulation the first one is RTL simulation which gives me the 1 cycle latency in read operation. And the second one is gate_level simulation with same bahavioural model of 1kb sram but it has half cycle latency. Will you please guide me that which behavior should I consider as true. Or I am doing something wrong.

What is the difference in the model you are using? We only provide a behavioral model...

I am using the same behavioral model with my RTL Simulation and gate_level Netlist simulation. But I am getting different behavior in both simulations with same behavioral model. Which is a confusing thing for me. That how same model behaves differently with gate_level simulation.

Yes, this is due to your address changing on the clock edge. One arrives before and the other arrives after..

Referring to the timing diagram given in the documentation of openram(sram). After providing the address and required read signals, memory takes half cycle to output data(half cycle read latency) am I getting it right??

Yes it needs the negative edge

Yes that's what I mean. Memory gets address at positive edge(or after positive edge if considering setup hold time) and outputs the data after negative edge of the same clock cycle.

I think there's a race condition in your simulation.

Thank you @Matthew Guthaus for your guidance. Let me try to resolve this.

@Matthew Guthaus Is it enough to allow changes on CE only on falling clock edges but let other signals (addr, data, ...) changing on rising edges to avoid race conditions in IC? If not - is it better to implement similar registering for all signals or invert clk given to openram?

@Paweł Sitarz you should be able to treat openram as a positive edge triggered flop. If you supply addr/data on the positive edge, you will get a result by the next positive edge.

@Matthew Guthaus Good, so delaying CE by half a cycle should be enough. I just wanted to avoid registering everything as DFFs are eating up space fast. Thanks!

@Paweł Sitarz I'm not clear what you mean. CSB? There is no CE.

@Matthew Guthaus Yes, I mean CSB, not CE.

That must arrive by the positive edge.