For my MPW-3 project, I have integrated 2KB SRAM hardmacro available from PDK path : sky130A/libs.ref/sky130_sram_macros. I see high number of DRC violation reported by magic tool with "Local interconnect spacing < 0.17um (li.3)" inside the SRAM Hard macro Any suggestion on how to manage this ?

See https://skywater-pdk.slack.com/archives/C016ULUQXDF/p1631097190005900