Gives me this error, Do i need set the no of cols including rbl(read bit line?) in my python config file?

Due to the replica bitline, you will likely need to add a spare column. The bitcell provided by Skywater can only be in multiples of two due to layout lithography issues.

ok so it gives me this error if i add num_spare_cols=1!

The same is true for the number of rows. You can look at some valid configs here: https://github.com/efabless/sky130_sram_macros/tree/main/configs

@Praveen raj, Is this issue resolved for you ? I am also facing same Error

ram_4kbyte_1rw_32x1024_8.py 
|==============================================================================|
|=========                      OpenRAM v1.1.19                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: <mailto:openram-user-group@ucsc.edu|openram-user-group@ucsc.edu>           =========|
|=========        Development help: <mailto:openram-dev-group@ucsc.edu|openram-dev-group@ucsc.edu>        =========|
|=========         Temp dir: /tmp/openram_dinesha_66698_temp/         =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 10/18/2021 16:56:46
Technology: sky130
Total size: 32768 bits
Word size: 32
Words: 1024
Banks: 1
Write size: 8
RW ports: 1
R-only ports: 0
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Only generating nominal corner timing.
ERROR: file sram_config.py: line 132: Invalid number of cols including rbl(s): 257. Total cols must be divisible by 2
Traceback (most recent call last):
  File "/home/dinesha/workarea/tools/source/OpenRAM/compiler/openram.py", line 54, in <module>
    c = sram_config(word_size=OPTS.word_size,
  File "/home/dinesha/workarea/tools/source/OpenRAM/compiler/sram/sram_config.py", line 44, in __init__
    self.compute_sizes()
  File "/home/dinesha/workarea/tools/source/OpenRAM/compiler/sram/sram_config.py", line 95, in compute_sizes
    self.recompute_sizes()
  File "/home/dinesha/workarea/tools/source/OpenRAM/compiler/sram/sram_config.py", line 132, in recompute_sizes
    debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, self.array_col_multiple), -1)
  File "/home/dinesha/workarea/tools/source/OpenRAM/compiler/debug.py", line 47, in error
    assert return_value == 0
AssertionError

I have used the example configs/sky130_sram_4kbyte_1rw_32x1024_8.py in https://github.com/efabless/sky130_sram_macros Still failing with same Error

yes add these line in the config file, num_spare_cols=1 num_spare_rows=1

Thanks, It worked🙏, I thought https://github.com/efabless/sky130_sram_macros configure are Sky130 working scripts