@User is there any stable released model of openram(sram) other than 1Kb model. Which doesn't have DRCs??

FWIW, the sram modules are installed to

$PDK_ROOT/sky130A/libs.ref/sky130_sram_macros

with

make pdk

in the

OpenLane

directory if you

export INSTALL_SRAM=YES

.

Is this give DRC and LVS clean SRAM ? I have tried compile one standalone RAM with below command python3 $OPENRAM_HOME/openram.py configs/sky130_sram_4kbyte_1rw_32x1024_8.py

WARNING: file magic.py: line 239: DRC Errors sky130_sram_4kbytes_1rw_32x1024_8	44

ERROR: file magic.py: line 349: sky130_sram_4kbytes_1rw_32x1024_8	LVS mismatch (results in /tmp/openram_dinesha_70719_temp/sky130_sram_4kbytes_1rw_32x1024_8.lvs.report)
** Verification: 51649.2 seconds
** SRAM creation: 53186.9 seconds
SP: Writing to /home/dinesha/workarea/efabless/MPW-3/sky130_sram_macros/macros/sky130_sram_4kbytes_1rw_32x1024_8/sky130_sram_4kbytes_1rw_32x1024_8.sp
** Spice writing: 1.4 seconds
GDS: Writing to /home/dinesha/workarea/efabless/MPW-3/sky130_sram_macros/macros/sky130_sram_4kbytes_1rw_32x1024_8/sky130_sram_4kbytes_1rw_32x1024_8.gds
** GDS: 124.5 seconds
LEF: Writing to /home/dinesha/workarea/efabless/MPW-3/sky130_sram_macros/macros/sky130_sram_4kbytes_1rw_32x1024_8/sky130_sram_4kbytes_1rw_32x1024_8.lef
** LEF: 0.0 seconds
LVS: Writing to /home/dinesha/workarea/efabless/MPW-3/sky130_sram_macros/macros/sky130_sram_4kbytes_1rw_32x1024_8/sky130_sram_4kbytes_1rw_32x1024_8.lvs.sp
** LVS writing: 0.1 seconds
LIB: Characterizing... 
** Characterization: 1.4 seconds
Config: Writing to /home/dinesha/workarea/efabless/MPW-3/sky130_sram_macros/macros/sky130_sram_4kbytes_1rw_32x1024_8/sky130_sram_4kbytes_1rw_32x1024_8.py
** Config: 0.0 seconds
Datasheet: Writing to /home/dinesha/workarea/efabless/MPW-3/sky130_sram_macros/macros/sky130_sram_4kbytes_1rw_32x1024_8/sky130_sram_4kbytes_1rw_32x1024_8.html
** Datasheet: 0.0 seconds
Verilog: Writing to /home/dinesha/workarea/efabless/MPW-3/sky130_sram_macros/macros/sky130_sram_4kbytes_1rw_32x1024_8/sky130_sram_4kbytes_1rw_32x1024_8.v
** Verilog: 0.0 seconds
** End: 53314.5 seconds

I see there are DRC and LVS Failures

The models that are already compiled in sram_macros repo also have drcs

@Sajjad Ahmed You can search slack for "sram drc" for known DRC issues and how they're dealt with.

To be a bit pedantic, they have DRC errors if you use the user design rules and not the core memory design rules. They are DRC clean with the core memory rules. The tools don't support the core memory rules so you need to replace with the LEF