<@U0175T39732> So i have generated the files for 5...
# openram
p
@User So i have generated the files for 512_18bit_1Kb from openram using this config.py, and here is the log file too! So how do i approach next step to get my sram block ready to be instantiate with Caravel by solving the drc errors and verification of it?
1. I do have the latest version of magic 8.3.220 but the LVS issue persists. 2. I also tried opening the gds file in magic to view the drc errors i get but it does not display any blocks i am getting a blank screen(but i can see the gds in klayout!)
m
I'm not sure about the LVS issue, but that is of concern and will require some debugging. I won't have time for a while, but you can file a ticket in the OpenRAM github You can look at the run_drc.sh file in the temp directory to see how to run DRC with magic.
p
alright will check that out!
m
FYI, I am using Magic 8.3.197. It is possible that there were more fixes to pin extraction that still don't work
Can you include your lvs report?
Copy code
/tmp/openram_praveen_2114_temp/sram_18_512_sky130.lvs.report
p
Seems like i cannot find that file..
m
Rerun openram with -k to keep the temporary files
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p
i only have the .lvs.sp
m
Oh, then it probably wasn't able to run netgen. Do you have netgen installed?
p
yes i do have
m
are there any .out or .err files?
p
no there isnt any
only these exists
m
Re-run with -k option to keep the temporary files. It seems that OpenRAM "succeded" (it still has DRC/LVS errors, but it will delete the temp files)
that is the output directory, not the temp directory
which is /tmp/openram_praveen_2114_temp
You showed me the contents of /home/praveen/OpenRAM/config_files/16x512_1KB_1/temp
p
ok got it but i also check /tmp/, ther isnt any folder as openramram_praveen_2114_tmp, so i need to use -k for that ?
m
Yes you need to use -k for that
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p
And will it take nearly this much time End: 8171.4 seconds to generate, and verify sram block usually?
m
Yep
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Magic is quite slow at extracting the layout for LVS
p
Hmm gotcha, !
m
Interestingly, klayout is faster and I've been trying to add support for that.
klayout is multithreaded
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p
Oh ok that's great!
here it is, getting the same LVS issue!
Ok so i tried to see some layouts in magic, and as u @User told i run the run_drc.sh , it generated some mag files, and i opened some and i had these kind of errors(images). So i was happy that it does make sense because in a youtube video with matt venn you just told that for magic DRC its gonna be only the metal layers which we check and i can see that! Here are my questions then, 1. So i got around 10 to 14 mag files(after running the sh file run_drc.sh) and i guess many of them have drc errors, so how should i actually approach with these, for getting a working sram ready? do i have to make these drc error free but after that how will the verilog and other files change according to my changes in the mag files if i did that.....it will really helpful if u can define a path for getting an sram block working after generating the files from the compiler ! Im really serious at generating them and will be happy to contribute by giving other sram macros(hopefully)! 2. And there are other sort of sh files like run_ext.sh., which i tried running and that throws a lot of mag file with the ext spice files for those also(so that also generated a sram_18_512_sky130.mag which magic just struggles to handle edits with 😞 ) but what are the other mag contribute to the core of this sram main mag file, because i can see sense amplifier, and precharge circuits mag files as one of them... 3. And what does the run_lvs.sh file do?
m
run_ext.sh runs converts the GDS to mag and runs extraction run_drc.sh runs DRC (and replaces the cells that have non-user design rules with LEF files with only metal) run_lvs.sh runs LVS You need to run them in that order. What you are showing looks like the LEF cells, but I'm not sure what those errors are. They don't look like real errors. Can you select and do a :drc why?
p
yeah so metal 1 is missing at the small portion in the third image mag file
m
Maybe do a :drc check to re-run DRC from scratch
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p
Ok i will do that, and i hope you saw the lvs.report file?
m
I didn't look yet. It is 6:45am here and I just got up
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p
Ohh im sorry, take ur time πŸ™‚ !
m
It looks like it is failing to extract the gnd net even on a basic inverter. This is likely a port issue in magic.
Subcircuit summary: Circuit 1: pinv |Circuit 2: pinv -------------------------------------------|------------------------------------------- sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1) sky130_fd_pr__pfet_01v8 (1) |sky130_fd_pr__pfet_01v8 (1) Number of devices: 2 |Number of devices: 2 Number of nets: 5 Mismatch |Number of nets: 4 Mismatch --------------------------------------------------------------------------------------- NET mismatches: Class fragments follow (with fanout counts): Circuit 1: pinv |Circuit 2: pinv --------------------------------------------------------------------------------------- Net: A |Net: A sky130_fd_pr__pfet_01v8/2 = 1 | sky130_fd_pr__pfet_01v8/2 = 1 sky130_fd_pr__nfet_01v8/2 = 1 | sky130_fd_pr__nfet_01v8/2 = 1 | Net: Z |Net: Z sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__pfet_01v8/(1|3) = 1 sky130_fd_pr__pfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1 | (no matching net) |Net: gnd | sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/4 = 1 ---------------------------------------------------------------------------------------
Can you confirm which magic and netgen you are using?
(It's probably best to debug with a tiny design too..)
If you can run that and send me the entire temp directory it would be useful
p
Sure im on to it!
here are the versions!
m
As I mentioned, I'm using magic 8.3.197. They might have re-introduced the bug on port extraction.
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I think that's the issue.
p
I had the same version before i think or probably .200, and i had same issue..
Running the tiny example, will update shortly!
So is the temp meaning the output directory or the /tmp/ ?
So yes im getting the lvs and the magic error, so waiting for ur reply on the directory ques!
m
The openram temp directory. You named your output directory tmp, that is not what I want. We output the temp directory at the start of openram: Temp dir: /home/mrg/temp/
(or a random name. You can define this if you set OPENRAM_TMP, but then you can only run one copy at a time)
I don't know if .200 works either
p
so this one /tmp/openram_praveen_2329_temp?
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meanwhile i downgrade my version of magic and check again
getting the same errors after changing the version too! will update you the /tmp/praveen_2329_temp files shortly
m
The good news is that it passes LVS for me: Circuits match with 36 symmetries. Resolving automorphisms by property value. Resolving automorphisms by pin name. Netlists match with 36 symmetries. Circuits match correctly. Result: Circuits match uniquely. Logging to file "sky130_sram_0kbytes_1rw1r_8x16_2.lvs.report" disabled LVS Done. So this must be something with your PDK setup
There are 16 DRC errors due to supply routing but those are somewhat expected and easy to fix
Do you get any errors when running run_ext.sh or run_drc.sh?
p
will try that now!
m
I'm trying with the newest open_pdks to see if anything broke it
p
how could i get the log file for the run_ext.sh?
it says it is finished but that some errors and warning in between
m
It just goes to stdout. So you can do something like: ./run_ext.sh | tee -i ext.log which will display it to stdout AND the log file
p
so here are the logs for the run
m
What are the errors?
p
Circuit 1 contains 2689 devices, Circuit 2 contains 2689 devices. Circuit 1 contains 922 nets, Circuit 2 contains 899 nets. * MISMATCH * Result: Cells failed matching, or top level cell failed pin matching. Logging to file "sky130_sram_0kbytes_1rw1r_8x16_2.lvs.report" disabled LVS Done. Saturday 23 October 2021 120438 AM IST: Finished (0) LVS using Netgen /usr/local/bin/netgen
m
I mean in the ext.log, the first step
The first error not the final
p
image.png
m
That should be ok. That is actually a warning.
p
image.png
m
Same
p
oh ok let me check
seems like there isnt any, but there are many errors with warning only
m
then that step is ok. What about the next step?
Work through it piece by piece...
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p
Processing timestamp mismatches: sky130_fd_bd_sram__openram_dp_cell_dummy, sky130_fd_bd_sram__openram_dp_cell_replica, sky130_fd_bd_sram__openram_dp_cell. Finished expanding Finished drc check Loading DRC CIF style. Finished drc catchup Total DRC errors found: 16 Saturday 23 October 2021 121023 AM IST: Finished (0) DRC using Magic /usr/local/bin/magic
m
That looks correct. The 16 errors are expected
The timestamp mismatch just means that the cells have different timestamps in the library
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We overwrote the extracted cells with the library cells before running DRC
p
this is when i run the lvs sh
seems like the sky130 devices arent deteted?
m
Those are ok because we end up ignoring properties in the setup.tcl.
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p
And this is the case at the end of lvs sh Circuit 1 contains 2689 devices, Circuit 2 contains 2689 devices. Circuit 1 contains 922 nets,Β Β Β  Circuit 2 contains 899 nets. * MISMATCH * Result: Cells failed matching, or top level cell failed pin matching. Logging to file "sky130_sram_0kbytes_1rw1r_8x16_2.lvs.report" disabled LVS Done. Saturday 23 October 2021 120438 AM IST: Finished (0) LVS using Netgen /usr/local/bin/netgen
m
Ok, now the results of that will be in the lvs.report
p
there are many mismatches like this
no matching net
m
So that is part of the problem but we need to deduce what is the cause.
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You can also look at the device output and see that the connection counts on the pins are different somewhere. If extra connections, that means there is a short. If there are missing connections, there is an open.
p
sure i will look into it, tomorrow as it is 12:30am here!
m
Here is how to read the results: http://opencircuitdesign.com/netgen/
Tutorial 2