Is it ok, that I've got 19 DRC errors in example design of sky130_sram_1kbyte_1r1w_8x1024_8.py?

These are all related to the power supply router which unfortunately has issues with some of the off grid pins. They are simple fixes though we would like to solve it in an automated way...

Thanks

My tip is turn off all DRC in openlane as it's a waste of time with openram. Then do the drc checks with the precheck.

In first post I told about DRCs, that were reported by Magic on standalone GDS of reference SRAM config and i'ts not clear, shold I ignore them or fix manually.

Ignore

Ok

@User Those DRC errors are after OpenRAM replaces the bitcells with maglef versions. Otherwise, the bitcells themselves will have many many more errors