@User I'm trying to understand a little bit the results from @User about OpenRAM and how that would affect our future designs (once a lot more test are done I guess) In the case of the output delay of around 10ns: Is that something that would be added to the srams liberty files? In that case the OL flow sta would warn us if we try to use it at faster clock speeds than we could?

This is not delay from the SRAM but delay from the output of the SRAM through the IO pad. The SRAM has very small output drivers which are currently driving a very long wire and then a BUF_8 which drives another VERY VERY long wire and then the IO pad. There are probably max slew warnings if STA was enabled.

Thanks. I understand better now the results from these testings by Andrew. I assumed there were mostly SRAM delays

@Matthew Guthaus So it's possible that with some kind of wrapper around / shim for OpenRAM, we can get better results, right? Should having CSB stable a 1.5 cycles before reading and all other signals 2 cycles before help?

@Paweł Sitarz Since they've enabled timing optimization and STA in the OpenLane flow, it will be automatically addressed now. This design was before the first MPW.

Hi @Maximo Balestrini, can you do me a favor and point me to the results you are refering. Would be interesting to read. Thank you in advance.

@Tobias Strauch I first saw something in twitter, but now there's a lot of info in #silicon-validation