Hi Andrew, thank you for your answer and for your great work. I remember, we already had a discussion on the silicon-validation channel. I was asking Matthew explicitly about the clock-high-time extracted from the simulation. It would be a waste of my submission, if my estimation of 2ns is way off, or my understanding is wrong - which is usually the case. Of course I will add a margin and embed the chip in a proper test environment inspired by yours. Your plots show the Fmax of the complete chip. With all due respect – and I stated it earlier already – I’m not convinced, that you can derive from them the Fmax of the SRAMs or the clock-high-time of SRAMs. Certainly the minimal boundary, as you already stated. In the very late 90’ we did R4000 RISCs at 250MHz in µ18 at LSI Logic with a lot of SRAMs ($, TLB, ...). The OpenRAM SRAMs might be less timing optimized, different node and fab etc., but I can roughly recall the SRAM timings of that time. @User Just a minimal clock-high-time value (if my understanding is correct) derived from the simulation would already be awesome and very helpful for my project. Thank you in advance.

As I've mentioned, we are using 50% duty cycle and don't have that measured.