I have a question about the memory readout delay. ...
# openramp
Po-Han Chen
02/11/2022, 7:05 PMI have a question about the memory readout delay. In the SRAM behavior model (.v) it sets a default delay value to be 3ns, but I checked the library file (.lib) it seems like the delay for the dout port is about 0.3ns~0.5ns, which looks like a registered output. I think I should trust the lib file but just want to double confirm that the delay for the SRAM read out is roughly at the scale of <1ns range
m
Matthew Guthaus
02/11/2022, 7:28 PMThe Verilog file also has a comment that it is arbitrary.
" // FIXME: This delay is arbitrary."
Matthew Guthaus
02/11/2022, 7:28 PMThe library files are not accurate right now. Don't trust them.
p
Po-Han Chen
02/11/2022, 7:41 PMI see. Do we have an expected day when the library numbers will be correct in the future release? Otherwise we can't do accurate STA on the path associate with the SRAMs
m
Matthew Guthaus
02/11/2022, 7:41 PMIt's on our list... I am being pullled 5 different ways and trying to get students up to speed too.
Matthew Guthaus
02/11/2022, 7:42 PMYou can set artificial constraints in the meantime with set-input-delay and set-output-delay.
p
Po-Han Chen
02/11/2022, 7:43 PMGotcha, thanks for the information!
d
Dinesh A
02/15/2022, 7:52 AM@User Is 2KB SRAM timing .lib available inside PDK_ROOT are also not correct ? in MPW-2/3/4/5 setup ?
m
Matthew Guthaus
02/15/2022, 1:22 PM@User they are all placeholders
d
Dinesh A
02/15/2022, 3:26 PMOops, My MPW project tightly linked with work of SRAM Model, I need to back-off SRAM integration in latest MPW Shuttle.
Dinesh A
02/17/2022, 5:18 PM@User From the SRAM behavior code, it look like SRAM capture data in Raising edge of clock ? Launch at falling edge of clock ? Is this correct design understanding ?
m
Matthew Guthaus
02/17/2022, 6:59 PM@User that is correct
5 Views