if I want to do gate level simulations with designs that include openram, is there a gatelevel verilog version of openram? I assume not, but I don't know how to proceed without one

@User Gate level simulation does not means, you need to use all the macros with netlist ... You can have some macro with netlist and other with rtl model. Typically full-chip gate-level simulation are slow. Standard industry approach is selectively pick netlist for some macro and rest with rtl model.

yeap. seems hard to pick and choose with the new caravel layout

Just wondering, would you be able to put a link to the openram behavioral (or rtl) verilog in the

verilog/gl

directory and do GL simulation with the current caravel setup?

Actually as an SRAM cell is not a digital cell one could even argue if a full gate level simulation of an SRAM block makes sense...

Yes, it's more that I can't use the verilog model that we have in GL tests as they are structured. So either I can provide a GL netlist or I can start hacking the makefiles / include files to make a mix of GL and RTL. Make sense?

What do you mean with GL tests ?

gate level tests

OK, I agree then that the PDK installation should provide the needed netlist to make these verify-<mytest>-gl work for the supported OpenRAM blocks. The verilog model could likely be a copy of the RTL model. (or not ?) I am a noob on the caravel flow as I am a caravan user...