How is the local interconnect different from a met...
# sky130
t
How is the local interconnect different from a metal layer ?
f
Hi Sylvain, local interconnect is polysilicon and forms the gate for cmos transistors. To increase transistor placement density, they also use the poly to wire up transistors (instead of going from poly to contact to metal1 and beyond - once you change from poly to metal 1, you incur a large area hit due to area overage for contact/via). High resistance is relative to metal, but because capacitance is typically low, you can manage the speed hit of the RC time constant. Hope this helps.
t
Incorrect. Local internconnect is Titanium Nitride (TiN) and is not used for CMOS gates, but is essentially a fairly high-resistance first-layer metal. The resistivity for Titanium Nitride falls between aluminum and polysilicon. Polysilicon is 48.2 ohms/square. TiN local internconnect is 12.2 ohms/square. Metal 1 is 0.125 ohms/square.
Typically, local interconnect is doubled up with metal1, as is the case with the power rails in all of the standard cells. There is an unchecked DRC rule that uncontacted local internconnect cannot have an aspect ratio of more than 10, which (if enforced) effectively prohibits the use of local interconnect for routing.
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t
What do you mean "not used for CMOS gates" ? I definitely see pretty much all the cells in the standard library using it. (and only resorting to metal 1 when there is no choice)
f
Sorry I tried to add value from previous ic design experience (I have taped out >20 analog mixed-signal chips, some in production), not from looking at the skywater pdk. I had never worked on a process with local interconnect (it's always been poly + metal for me), but Tim is right and I stand corrected.
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