So in the std cells, the

nwell.pin

and

pwell.pin

are the connections from the

li

layer to the bulk (either the n-well or the p-substrate). I'm a bit surprised there is only 1 per cell though, I thought there would be a bunch equally spaced like the

mcon

between the

li

and

met1

carrying the power rails.

Haven’t look at the layouts, but for insulated wells it’s likely enough to meet latchup rule, if the well is shared you will need to add tap cells as required

@tnt: In the standard cells, there are no connections to bulk (except in the high voltage library). In this kind of standard cell, the layout is made tighter by not putting contacts to well and substrate in the cell itself. It is the responsibility of the synthesis flow to insert the "tap" cells such that they meet the required latchup rule (< 15um) for the spacing between a tap (as meaured from the tap contact center) and any diffusion.

Oh ok, interesting.

Do you mean for the logic view or on layout? Even if there is no pin for bulk inside the standard cells, it is common for logic models to include substrate pin (device_layer type), this is useful to perform static checks to verify you are in compliance with substrate connection applied to your voltage area which will apply due to abutment.

Yeah I meant in the std cell libraries in the GDS they have a square drawn in those layers. I was wondering why. But if it's for some compliance check ok.