@User We are also trying to change the way people think about doing ASIC design -- just like there is the idea in software that "master is always green" -- it would be good if designs where "master is always ready to be sent to production" -- get something that works and then optimize it second

I agree in principle, and that's what I generally try to get my students to do. But especially in analog design, there is a couple of days worth of manual work at the end (metal fill, antenna violations), so we wind up closer to a 'master is always almost green'. So the risk of not being ready when TO rolls around I think is fairly low. But the work of just getting up and running on the process is enough that doing that, then not getting a slot is a bummer.