@User I'm not sure what that is, I know there is work on getting better parasitics extraction and stuff going

This is for pre-layout timing. Generally, .libs have WLM (wire-load model) definition (latest tech nodes, might not have those). Since this is 130nm, we were looking for WLM definition for analysing pre-layout performance.

Maybe you can try extracting interconnects instead? openlane mentions DEF2SPEF, but I haven’t tried. https://github.com/ehossam/def2spef

This is already working. We were looking to compare results pre-layout and post-layout (using SPEF). And expectation is post-layout should give more arrival time than pre-layout due to addition of parasitics. This data point helps characterize and quantify the impact of spefs which can be referred to later for analysis, if something goes wrong in final sign-off analysis. This also helps to understand the quality of clock tree. Currently we are seeing skew of ~1ns which is 10% of clock period. Data arrival time is around 9ns with spefs