@User -- I would love to see the stuff you have at http://diychip.org/sky130/ merged into the docs I just added at https://github.com/google/skywater-pdk/blob/master/docs/contents/libraries/foundry-provided.rst

@Tim 'mithro' Ansell Thanks for that doc! It has useful clarifications and design rational I was trying to infer from the library data. I am looking carefully at what I might have said that adds to it. My first reflex is to gather up some of the textual information you provide into a few more columns of my table. I am slightly concerned it will make something quite wide but it is probably worth it. There is an interesting statement I would love some clarification about: “Blocks should be DRC clean when intermingled with :lib:`sky130_fd_sc_hd` cells.” Can I conclude that one can intermingle hd and hdll cells or does it mean I have to make sure the hdll cells are DRC clean before considering combining with hd? It’s a bit hard to figure out how to translate this into an openflow workflow.