@User: So, back to your "is it fine?" question: It is possible to connect the I/O pad this way for verilog simulation; just be aware that there are multiple power supplies and signals ending in "h" are on a 3.3V (VDDIO/VDDA) domain. In a physical layout, you would want to simulate with power pins enabled, and you would need to level shift signals as needed for the appropriate domain. analog_sel(), analog_pol(), and analog_en() should be tied low, not left floating. enable_inp_h should be grounded (on the 3.3V domain). HOWEVER---if this is outside the context of the Caravel chip, then your best bet, I think is to use one of the power pad base cells. These have a direct connection from pad to core (through a "short" metal resistor, so different net names, but effectively a straight-through connection). The cells contain voltage clamps, but the voltage clamps are not connected in the base cell, and the base cell does not connect the pad to any of the power rails in the padframe rings (there's an overlay cell for that).

@Tim Edwards What would be the disadvantage of using the analog pins? It would be simpler to avoid loading FW only to set GPIO configuration.

@James A: The only disadvantage would be if you absolutely cannot tolerate 150 ohms in the path. There are definitely circumstances when that would be true.