Can someone remind me what the

conb

cells are ?

The HI pin is tied to VPWR through a poly resistor. The LO pin is tied to VGND through a poly resistor.

Thanks. Do you know at which step they get inserted ?

No idea. Probably synthesis?

I don't think so, they're are neatly arranged in equidistant interval on the bottom so look like a dedicated step

That may be true. Although, you can find them in all the synthesis verilog outputs.

mmm, no I thikn the regular pattern was just because they are used to ties unused IO lows and so it placed one next to each IO ... whch are equally spaced.

That makes sense.

What doesn't is why they got place off-grid 😕

aren't these cells used to provide logic 1 and 0 where needed (may be as options) into gates?

yeah, they're used as "tie high" / "tie low".

Probably standard cell floor planning?