@User: to use gpiov2 and PG pad cells as verilog black boxes in openlane for synthesis , which verilog file is to be used

@Roshan Khatri: What are you trying to do? Build

chip_io

?

SoC for PLL

@Ahmed Ghazy: Sorry, I should have mentioned that Roshan was making queries about the I/O cells for the purpose of making his own padframe and design, not related to Caravel or the open MPW.

@Roshan Khatri, @Tim Edwards: Oh I see; then you may want to use

libs.ref/sky130_fd_io/verilog/sky130_ef_io.v

,

libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v

. If you want to use the original pads without the overlays then you want to check

libs.ref/sky130_fd_io/verilog/sky130_fd_io.v

. Some of the modules aren't parsable by yosys yet due to some simulation-related constructs being used there; if you are interested only in blackboxes of those IOs, you can find them directly at

skywater-pdk/libraries/sky130_fd_io/v0.2.1/cells/top_ground_hvc_wpad/sky130_fd_io__top_ground_hvc_wpad.blackbox.v

for example.

@Ahmed Ghazy I should include the .blackbox.v files in top level .v file