I'm not sure you can "show" metastability. A simul...
# sky130
I'm not sure you can "show" metastability. A simulation will always resolve one way or another due to numerical inaccuracies and stability of the simulator. Instead it will likely just show as a setup or hold failure. (Also sounds like a question for #vlsi101 !)
I'm not sure I understand. Is this a fundamental or physical limitation. Or a limitation of the tooling that can be resolved with better numerics and underlying models?
It's an issue that nobody tries to model it in simulation. Since it is highly affected by variability, it would be very difficult to have something meaningful. If you don't care about the variability, a spice simulator could technically model something but I believe that numerical inaccuracies would come into play...
In short, a small change can have a large effect in such a bistable system.
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cc @Keno Fischer
I want to add that on a real chip you also won
(Sorry) Want to add that on a real chip you also never will see a latch in the metastable state due to noise generated by currents. You actually have demonstrated how metastability will be seen in reality, and that is that the clk->q delay becomes longer if input signal transistion is close to the setup time.
I made a better animation showing hold timing metastability as well. And also got a much faster simulation by learning about looping in spice: https://twitter.com/matthewvenn/status/1343263618670981122
the spice model of the flipflop is from the sky130 pdk. are these generated by magic? I notice they don't include any parasitics. I wonder how much including these would change the simulation
would I need to load the cell in magic and then just extract it again with parasitics turned on?