Just tried my hands at making a ROM cell I can fit...
# sky130
t
Just tried my hands at making a ROM cell I can fit in the standard cell grid. 🙂
👍 5
✔️ 1
t
I fail to see how this thing works, though. . . I see four nFETs, grounded drain, sources tied in pairs, and individually controlled gates. I don't see how to read out a value.
t
So I'm implementing something like

http://www.csit-sun.pub.ro/courses/vlsi/CursVLSI/www.lesia.insa-toulouse.fr/_bendhia/Cours/CMOS/images/memory49.jpg

The cell is just the nFET, in groups of 4s. The sources should actually be wired, that screenshot didn't have that. And they are the vertical bitline. They can be either connected or not, just by changing
met1
to set the rom content. The gates are wired to the 4 word lines running all along horizontally. On the "top" there needs to be pull-ups / pre-charge to set the bitlines high if nothing is forcing them down. And on the "bottom", a buffer that will read the actual value and provide the required drive strength to actually drive logic. Of course it's also completely possible I misunderstood fundamentally how this is supposed to work 😅
t
I'm sure it's fine. Precharging circuits are always confusing to look at, especially if you're not seeing the precharging part of it.