What is the EDA tool flow to do full custom design? Is there a git repo with example for this?

Meaning full-custom analog?

Yes

I suggest using xschem (#xschem) for schematic entry and schematic capture, ngspice for simulation (this is well-integrated into xschem, along with the "gaw" waveform viewer), and magic (#magic) for layout and extraction.

@Darshak Doshi for full custom analog, if you decide to land on xschem you must install xschem, then the xschem libraries/component/symbols specifically targeted to the skywater process and the ngspice simulator. My suggestion is to install from sources all these packages so you get the most updated ones, (this skywater project is very new and in rapid evolution). This video tutorial may be useful to make all the tools work well together.

Thanks ! Appreciate the help

hi, @Darshak Doshi, see this video at 26'45", you need to tell xschem how to start ngspice. If ngspice is not under a directory specified in your PATH environmental variable specify the full ngspice path name in xschem 's Simulation->Configure simulators and tools.

I definitely have the ngspice in my environment PATH, I am seeing some warnings when I start my xschem, maybe its related. I also see the test_nmos as test_nmos.sym , which wasn't the case earlier. I don't know if this snippet helps, but you can take a look. Appreciate your help on this.

@Darshak Doshi are you sure you don't have an older xschem installation? My advice (may be you already did so, just to be sure) is to install xschem from the git repository, and remove old xschem executables and old .../share/xschem directories.

Thanks for all the help. I resolved all the issues. Newer version fixed the warning problem, and the ngspice invoking was because somehow xterm was not installed in my system. Follow up question, once I have schematic and simulation, how do I take it to magic? Is there a standard format xschem dumps out file that is accepted by magic? Is there a flow with example?

@Darshak Doshi for analog full custom designs there is no automatic layout generation. You have to draw transistors/other devices and interconnections, following the process design rules. DRC checks (Design Rule Checks) are present to highlight design rule violations (minimum spacing, width, length, overlap etc). When done a netlist can be extracted from the layout and compared (LVS, Lavout Vs Schematic) with the xschem schematic netlist. For digital design there is an automatic flow from HDL (Verilog) all the way to layout (GDSII) (search for OpenLane), in this case you don't need a schematic editor at all.