I have a few questions about the behavioral models for the PDK. 1/- what's the status on these 2 issues: https://github.com/google/skywater-pdk/issues/292 & https://github.com/google/skywater-pdk/issues/297 ? They seem to fairly serious for GL simulation. I am not hitting them with my PDK install, but people on my course are. 2/- what's the reasoning behind the FUNCTIONAL flag? I see it set in the Caravel testbenches though it doesn't always seems to be needed.

Issue 297 is fixed by the open_pdks installation. I'm still waiting on @Tim 'mithro' Ansell to make it possible to do pull requests on the base libraries so this can be fixed in the PDK instead of patched by various tools. Issue 292 I did not know about. In the original sources, the "delayed" signals are driven from "$setuphold" lines in the verilog. Timing statements like "$setuphold" are not implemented in iverilog. This was dealt with by removing the "specify" sections from the verilog. It appears that in most cases the "specify" section just annotates the design with additional timing information. Unfortunately in the case of some of the cells, the correct netlist is dependent on the timing statements, and the timing description is not merely an annotation of the (otherwise correct) netlist. The FUNCTIONAL flag is (apparently) what works around this issue; the ".functional" verilog models differ from the ".behavioral" in not having timing information, and so the problem with the missing statements does not arise. Using this flag allows gate-level simulation with verilog for the flip-flops.

Thanks Tim!

FYI, Tim Ansell just pushed pull request #303 on skywater-pdk, making all submodules into git repos, such that all problems where a solution is immediately available can be handled with a pull request to the appropriate github repository.