I am currently in the process of learning the desi...
# sky130
I am currently in the process of learning the design flow for the PDK and while I was browsing the documentation, I couldn't find anything regarding the maximum frequencies for each part. Did I miss something? I also saw that there were SONOS cells available. Is there a specific way to make a design using them in Verilog? Do I need to specify that in the constraints? The flow I am using is OpenLANE if that makes a difference.
It's not really possible to give a maximum frequency value because that depends on a lot of factors
But from my notes, a FO4 inverter is 66ps on fd_sc_hs, and 76ps on fd_sc_hd
Okay, so it is all about if the simulation says it is good for things like clock buffers and I/O?
Also: The SONOS cells are for NVRAM and require a lot of support circuitry. You won't find those in any standard cells. At the moment you won't find them anywhere since we don't have the supporting circuits and will have to figure out how to design them ourselves. The intention is that memory cells with SONOS transistors will be part of a library that you can use with OpenRAM to build nonvolatile memory blocks. But don't hold your breath---it will take a lot of design, testing, and several iterations to work it all out.
@Tim Edwards thank you for the information about SONOS cells, I will keep an eye out on future releases.
@Tim Edwards I'd be interested in helping with the SONOS cells if possible. I've got prior tapeout experience (I did my grad school with Gert ). I'd be happy to lend a hand :)