Amro Tork
04/18/2021, 4:09 PMTim Edwards
04/18/2021, 6:14 PMAmro Tork
04/18/2021, 8:06 PMAmro Tork
04/18/2021, 8:06 PMCan Wang
04/18/2021, 8:45 PMAmro Tork
04/18/2021, 9:32 PMAmro Tork
04/18/2021, 9:33 PMTim Edwards
04/18/2021, 9:45 PMsky130_fd_io__top_power_hvc_wpadv2
, which without an overlay cell is just a straight-through connection from pad to core, with a high voltage (3.3-5V) ESD clamp (unconnected) in the same cell under the pad. Because the clamp is directly under the pad, it is limiting the bandwidth of the circuit. So the project will take that pad and remove the clamp circuit from it, and any additional metal under the pad or close to it that is limiting the bandwidth. The sky130_fd_io library actually has a cell called sky130_fd_io__analog_pad
but it has only a verilog module and nothing else. So my suggestion was to make the modified pad layout the analog_pad
layout and schematic.Amro Tork
04/18/2021, 9:54 PMCan Wang
04/19/2021, 12:44 AMAmro Tork
04/19/2021, 12:59 AM