Hi, got out my fpga again recently and building a riscv core. I was wondering what is possible to do in a 130nm process. The pentium 3 was clocked at 1GHz, is that achievable on skywater? So you could easily do usb1 maybe usb2 but no usb3

The 130nm Pentium 4 ran up to 3.8GHz, but it took 100s of engineers several years to achieve this. You can't hope for the same results by throwing a Verilog file into a tool and getting a result in a few minutes. Note that each project in the shuttle already includes a RISC-V processor, though it is not one optimized for speed.

The picorv32. How fast did that one run? I guess at those speeds you have a temperature problem. Anyway mostly just doing it for fun and interested to learn more about electronics. I'm primarily a software engineer

The standard cells are very conservative so building everything on top of them will results in conservative circuits. If you replace the standard cell flip-flops with a custom register design, for example, you will get a faster processor. Replacing the finite state machines with ones based on PLAs could also improve performance. The reports from the STA (static timing analysis) should give you a very crude idea of how fast a design can run.

You want to expect around 30-50 MHz range, not GHz. Also Caravel goes up to 50M while your external bus will be pin limited (or limited by internal SRAM area) as well as limited by the ~30M of the external IO pads (depending on how you push it).

with PLLs the clock can be scaled up

@David Craven: A very carefully designed processor that doesn't overload the combinational paths with long logic chains can be expected to achieve maybe 200MHz maximum. If you used the high speed logic library you might be able to push that up to 250MHz. I am expecting the Caravel PicoRV32 processor to run at around 125MHz (it is not carefully designed because speed was not my goal).

What is the limiting factor? Transistor switching speed, power dissipation or something else?

The limiting factor would be transistor switching speed.

I understood it to be "150nm drawn, 130nm fabricated channel length". During diffusion the P and N regions grown down but also a bit to the sides making the channel a little narrower than the gate

It is certainly possible but I cannot find any reference to drawn channel length vs. effective channel length anywhere in the documentation. The models all appear to be based on exact L and W as specified in the parameters.

right, the spice models all are full of "l=150000u" in them

Well, the

150000u

syntax is from magic, so those would be extracted subcircuits, not models. But the models (e.g.,

.pm3.spice

files) have references to monte carlo mismatch parameters that depend on area, which are being calculated simply as

l*w

. Sometimes (in other foundry processes) I see models with

leff

used, where

leff < l

due to channel length reduction during manufacturing, as you were referring to.