Ke-Haur Taur
07/01/2021, 5:02 PM\rst_buf[2]
) of this clock buffer (sky130_fd_sc_hd__dfrtp_1
) for the reset is unknown, hence everything is not reset properly.
159294 sky130_fd_sc_hd__dfrtp_1 _45866_ (
159295 .CLK(clk_i),
159296 .D(rst_ni),
159297 .Q(\rst_buf[2] ),
159298 .RESET_B(rst_ni)
Corresponding waveform is shown belowDan Fritchman
07/01/2021, 5:21 PMFUNCTIONAL
flag enable, as described here: https://github.com/google/skywater-pdk/issues/310Sajjad Ahmed
07/01/2021, 8:15 PMTim Edwards
07/02/2021, 2:20 AMKe-Haur Taur
07/03/2021, 12:44 PMKe-Haur Taur
07/03/2021, 12:45 PMSajjad Ahmed
07/03/2021, 12:46 PMKe-Haur Taur
07/03/2021, 12:46 PMKe-Haur Taur
07/03/2021, 12:54 PMError-[SE] Syntax error
Following verilog source has syntax error :
"sky130_fd_sc_hd.v", 49280: token is 'module'
module sky130_fd_sc_hd__lpflow_bleeder_1 (
Relevant source code:
49279 `celldefine
49280 module sky130_fd_sc_hd__lpflow_bleeder_1 (
49281 SHORT
49282 );
49283
49284 input SHORT;
49285
49286 // Voltage supply signals
49287 wire VPWR;
49288 supply0 VGND;
49289 supply1 VPB ;
49290 supply0 VNB ;
49291
49292 sky130_fd_sc_hd__lpflow_bleeder base (
49293 .SHORT(SHORT)
49294 );
49295
49296 endmodule
49297 `endcelldefine
Did this happen to you also? @Sajjad AhmedKe-Haur Taur
07/03/2021, 2:53 PMmehdi
07/03/2021, 3:03 PMKe-Haur Taur
07/04/2021, 11:44 AMmehdi
07/04/2021, 11:49 AMKe-Haur Taur
07/04/2021, 11:55 AMDinesh A
07/06/2021, 10:28 AMSyntax error
Following verilog source has syntax error
I notice there is Typo in sky130_dc_hd.v at Line No: 102454
`endif SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
This need to changed as
`endif //SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
Due to this tool was reporting error in next module definationmehdi
07/06/2021, 1:18 PMDinesh A
07/06/2021, 2:40 PM