hello to all, I have a problem when I try to do a GL simulation using iverilog (RTL sim is done). I synthesize my file with yosys using the pdk lib, generate the netlist, and generate the verilog_net file. But when I try to do the testbench using the verilog_net file generated by yosys I get errors the commands were:

//open yosys
$ yosys
//read the library 
$ read_liberty -lib ../sky130_fd_sc_hd__tt_025C_1v80.lib
//read theverilog code
$ read_verilog Abs.v
//Synthesis process
$ synth -top Abs
//netlist generation
$ abc -liberty ../sky130_fd_sc_hd__tt_025C_1v80.lib
//write the netlist file
$ write_verilog -noattr abs_net.v
// close yosys 
$ exit

Now on the terminal

iverilog ../primitives.v ../sky130_fd_sc_hd.v abs_net.v tb_abs.v

And I get these errors:

../sky130_fd_sc_hd.v:37285: syntax error
../sky130_fd_sc_hd.v:37285: error: invalid module item.

can anyone help me with this?

How old is your pdk? This definitely was a problem a while ago

commit 6905a12d2efe18502c37c3207b5ee84cdf720d9c (grafted, HEAD, tag: 2021.09.19_20.25.16)

It's in my open_pdks install, too. I thought I had a patch for that.

@Tim Edwards Yes, now it's working. Thank you!

I apparently did not make a patch file for that error, so I'll go add that now.

Hello @Tim Edwards and @Matt Venn. I work with Mauricio and we have some troubles to verify our design aat the GL level. The question is if we have to specify some additional parameters of the synthesis in order to generate the top level module (an equivalent of regular user_project_example.v). Now we use