Has anyone done gatelevel netlist simulations with the verilog output from OpenLANE? I've been trying to get it working without any sucess using Icarus Verilog. Specifically, openLane instantiates flip-flops using the

sky130_fd_sc_hd__dfxtp

module, which then instantiates the primitive

sky130_fd_sc_hd__udp_dff$P_pp$PG$N

but doesn't actually make any connections between the two, meaning the simulation doesn't work. Trying a very simple 11-primitive netlist, the schematic openLane generates seems good, having sketched it out and followed the logic through manually - it just doesn't seem to be simulateable. Specifically, using the install of SKY130 that came with OpenLane, my design instantiates several D flops, so I pointed icarus at the gatelevel netlist and these two files:

sky130A/libfs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v

and

sky130A/libfs.ref/sky130_fd_sc_hd/verilog/primitives.v

. My netlist then instantiates this flop:

module sky130_fd_sc_hd__dfxtp (
    Q  ,
    CLK,
    D
);

    // Module ports
    output Q  ;
    input  CLK;
    input  D  ;

    // Module supplies
    supply1 VPWR;
    supply0 VGND;
    supply1 VPB ;
    supply0 VNB ;

    // Local signals
    wire buf_Q      ;
    reg  notifier   ;
    wire D_delayed  ;
    wire CLK_delayed;
    wire awake      ;

    //                                 Name  Output  Other arguments
    sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
    assign awake = ( VPWR === 1'b1 );
    buf                                buf0 (Q     , buf_Q                                       );

endmodule

You can see the issue here - unless I'm misunderstanding the verilog, the wire

CLK_delayed

is left unconnected, so the primitive which actually handles the logic never sees any input (and icarus bears this out -

CLK_delayed

is simulated as constant

x

). Is this the correct way to be doing simulations, or sky130 not suitable for simulations, or is this an actual bug I've found?

I have done some GL with skywater pdk. https://github.com/mattvenn/gate_level_simulation

@User Please take a look at this thread in the #ieee-sscs-dc-21q3 channel. https://skywater-pdk.slack.com/archives/C027VASS00L/p1635175665018300

I have run the gate level during MPW-2 submission. Initially i too faced same issue .. As i remembered issue was related to power supply hook up at test bench and propagating it to each module. Issue resolved after Running gate level simulation with 1. `define USE_POWER_PINS in uprj_netlists.v or Add -DUSE_POWER_PINS in iverilog compile command 2. Make sure that in Testbench top, Power supply is hook to DUT and inside DUT Power supply hook to each Module. Easyway to debug is create a small netlist + Testbench

@User I think the issue is that the input ports are not connected to any internal wires at all. The internal wires are the ones which are influenced by the user defined primitives.

Do you mean Power hook up connectivity missing ? OR Functional connectivity ?

functional connectivity

@User thanks for the link to your GL sims - I tried using that setup and found the same issue as before. If I understand it correctly, it just uses cocotb & declares some of the macros - I don't think that would fix the underlying issue @User and I have found, that the flop primitives are not being connected to their wrapper. If the simulations did work for you in the past, do you remember what version of sky130 it was so I can go and try that instead?

when you run my demo does it work?

@User your demo does work and I just got my code working too (!). I'd been trying to simulate the output from yosys (the .synthesis.v files). However,copying your demo, I tried simulating the output from later down the chain after LVS, using the lvs.powered.v gatelist, and it worked straight away.

I've never tried that.

@User Did to run the netlist simulation with -DFUNCTIONAL switch? .. My netlist simulation works well for both yosys and lvs netlist

In my case, I added the following two define to my testbench and it works: `define UNIT_DELAY #1 `define FUNCTIONAL