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Hi all, I have a very similar issue to the one rep...
# sky130
k
Hi all, I have a very similar issue to the one reported here https://github.com/The-OpenROAD-Project/OpenLane/issues/554 however I use sky130_fd_sc_hd cells. In general it reports a lot of overlaps
t
Generally this doesn't happen unless you have macros in your design. If you read the design into magic with macros abstracted, it should show errors where routes are overlapping obstruction layers in the macro, assuming that's the cause.
k
Thank You for Your response @User yes I have macros instantiated, I suppose that there exists some way to mitigate those overlaps
t
You would need to ask the Openlane developers whether this is an actual issue or if there is something you can do to your configuration. This is something that would normally be handled automatically by the tools.
k
ok, Thank You
@User searching the logs I found this
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[WARNING]: Specifying a routing obstruction is now done using the coordinates
[WARNING]: of its bounding box instead of the now deprecated (x, y, size_x, size_y).
[INFO]: Obstructions added over met5 0 0 2500 3200
in fact the way I changed the flow to pass the flow was to extract spice from GDS not from LEF
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[INFO]: Running Magic Spice Export from GDS...
[INFO]: current step index: 41
[INFO]: No Illegal overlaps detected during extraction.
[INFO]: Running GDS LVS...
It passes however it produces a lot of LVS mismatches
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net count difference = 169881
    unmatched nets = 1524
Total errors = 171475
all on nets, the device count matches
do You think it has something in common?
t
I'd have to see the whole LVS output file.
k
Hi @User I will send it to You right now
top.lvs.gds.log
top.lvs.gds.log
I have limited the number of macros to 1, the orginal project instantiates 34
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Magic DRC Summary:
Source: /openlane/designs/tt/runs/RUN_2021.11.05_13.12.22/reports/magic/43-magic.drc
Violation Message "Via1 spacing < 0.06um (via.2 - 2 * via.4a) "found 569 Times.
Violation Message "N-well spacing < 1.27um (nwell.2a) "found 94 Times.
Violation Message "This layer can't abut or partially overlap between subcells "found 8789 Times.
Violation Message "Metal2 spacing < 0.14um (met2.2) "found 6853 Times.
Violation Message "Metal1 spacing < 0.14um (met1.2) "found 46740 Times.
Violation Message "N-well width < 0.84um (nwell.1) "found 32 Times.
Violation Message "Min area of metal1 holes > 0.14um^2 (met1.7) "found 10 Times.
Violation Message "via2 width < 0.28um (via2.1a + 2 * via2.4) "found 117 Times.
Violation Message "All nwells must contain metal-connected N+ taps (nwell.4) "found 637 Times.
Violation Message "Metal3 spacing < 0.3um (met3.2) "found 1741 Times.
Violation Message "Metal3 width < 0.3um (met3.1) "found 3 Times.
Violation Message "P-diff distance to N-tap must be < 15.0um (LU.3) "found 2738 Times.
Violation Message "Via1 width < 0.26um (via.1a + 2 * via.4a) "found 858 Times.
Violation Message "Metal2 width < 0.14um (met2.1) "found 2 Times.
Violation Message "via2 spacing < 0.12um (via2.2 - 2 * via2.4) "found 405 Times.
Violation Message "HVI to HVI or LV nwell spacing < 0.7um (hvi.5) "found 150 Times.
Violation Message "N-diff distance to P-tap must be < 15.0um (LU.2) "found 2642 Times.
Total Magic DRC violations is 72380
----------------------------------------

LVS Summary:
Source: /openlane/designs/tt/runs/RUN_2021.11.05_13.12.22/results/lvs/top.lvs_parsed.gds.log
    net count difference = 4535
    unmatched nets = 103
Total errors = 4661
----------------------------------------
t
@User: There are several problems here; the first is that there is a difference in the number of diode cells in "top". Possibly that would be due to one of the netlists not reflecting changes made to resolve antenna errors; diode cells that are unused for tie-downs get merged into a single device by parallel combination, while all the diode cells used as tie-downs are counted individually. The bigger issue, though, is that the macro is totally screwed up in a way that I don't really understand. If you can tarball up the two netlists, I'd like to take a look.
k
ok, let me do it
one question, where does the OpenLane dumps the netlists ?
I can see the *ext files and the respective gds and lef
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puts "Reading spice netlist file /home/icarosix/asictoolchain/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
readnet spice /home/icarosix/asictoolchain/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice 1
lvs {/openlane/designs/tt/runs/RUN_2021.11.05_13.12.22/results/magic/top.gds.spice top} {/openlane/designs/tt/runs/RUN_2021.11.05_13.12.22/results/lvs/top.lvs.powered.v top} /home/icarosix/asictoolchain/OpenLane/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl /openlane/designs/tt/runs/RUN_2021.11.05_13.12.22/results/lvs/top.lvs.gds.log -json
top.lvs.powered.v
top.lvs.powered.v
so here is the "schematic"
do You need the gds as well ?
As for the macro it passes LVS and DRC without issues
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Magic DRC Summary:
Source: /openlane/designs/SSCS-SoC/runs/RUN_2021.11.02_17.19.14/reports/magic/36-magic.drc
Total Magic DRC violations is 0
----------------------------------------

LVS Summary:
Source: /openlane/designs/SSCS-SoC/runs/RUN_2021.11.02_17.19.14/results/lvs/SonarOnChip.lvs_parsed.lef.log
LVS reports no net, device, pin, or property mismatches.
Total errors = 0
----------------------------------------

Antenna Summary:
Source: /openlane/designs/SSCS-SoC/runs/RUN_2021.11.02_17.19.14/reports/routing/38-antenna.rpt
Number of pins violated: 8
Number of nets violated: 8
except the antenna violations
t
It could be an issue with the verilog parser in netgen. Can you post the SPICE netlist from the layout that it is being compared against (better than the GDS, since then I'd have to go to the trouble of extracting it)?
k
ok, the question is where the OpenLane dumps it ?
top.gds.spice
top.gds.spice
t
I think the verilog parser in netgen is not handling the net bundles on the SonarOnChip macro inputs properly. It is supposed to, so hopefully it is just some minor bug I can track down. At any rate, the main issue here seems to be a netgen parser error.
k
ok, hope You are right!
Thank You !
t
Thanks for providing the example files.
k
What about the prechecks on the efabless platform, will it pass it ?
t
It should; the precheck does not do LVS, and this issue is restricted to netgen as far as I can tell.
k
ok, soon I will have information about that so I will share
Thank You once more. BTW I am very impressed by Your contribution into the open circuit design, keep going !
t
Oops, wrong column. The problem is in the layout netlist, not the verilog netlist. The layout netlist has somehow managed to promote all subcircuit pins of SonarOnChip to the top level of SonarOnChip. That looks more like something that could possibly have been caused by a recent commit to magic. What version of magic are you using, and can you please provide the GDS as you originally offered?
k
let me check the version
8.3.216
yes of course I can share the GDS
SonarOnChip.zip
SonarOnChip.zip
top.zip
top.zip
SonarOnChip is a gds of the macro instantiated within the top.gds
t
Oh, crud, I broke magic. . .
Looks like 8.3.214 broke it. Try using 8.3.213 while I desperately try to fix this. . .
k
ok lest give it a try
@User in fact the magic version used by the flow is the one from the docker image
8.3.209
t
@User: Okay, what I found was this: The problem is in the layout; it is not an issue with either magic or netgen. If you look closely at the layout, you will see that the SonarOnChip macro is shifted such that the metal1 power rails drawn over the whole layout at the top level are misaligned with the power rails in the standard cells in SonarOnChip, and so power and ground are shorted and colliding with thousands of internal nets. So the clue is that in the top.spice file, the definition for SonarOnChip added many extra nets as ports, and the call to SonarOnChip in top connected all those ports to ground, indicating a massive number of shorts between the cell's internal nets and the top-level cell's ground. Now I am not sure what causes the macro to be shifted, but unless it can be shown that magic is mishandling an offset between the LEF and GDS of the macro (which is a possibility), then it should be treated as an error in Openlane. If you would like me to double-check the possibility of an offset issue, please post the LEF file of SonarOnChip.
k
@User cool, that is a good information for You I hope. Here goes the LEF file
SonarOnChip.lef
SonarOnChip.lef
In fact what I am doing is placing the macro manually using macro,cfg file.
soc1 90 20 N
Do You know how to place is in a correct aligned way ?
The other thing is that when I "build " the macro I got this:
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[WARNING]: Current core area is too small for a power grid
[WARNING]: !!! THE POWER GRID WILL BE MINIMIZED. !!!
t
This is an openlane message, presumably from the power distribution network generator, so I don't know what the implications are. For that and also for the alignment issue, I suggest you contact the openlane developers.
k
ok, thank You
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Magic DRC Summary:
Source: /openlane/designs/tt/runs/RUN_2021.11.05_21.51.38/reports/magic/43-magic.drc
Violation Message "Via1 spacing < 0.06um (via.2 - 2 * via.4a) "found 5 Times.
Violation Message "N-well spacing < 1.27um (nwell.2a) "found 96 Times.
Violation Message "This layer can't abut or partially overlap between subcells "found 6677 Times.
Violation Message "Metal2 spacing < 0.14um (met2.2) "found 2707 Times.
Violation Message "N-well width < 0.84um (nwell.1) "found 28 Times.
Violation Message "All nwells must contain metal-connected N+ taps (nwell.4) "found 628 Times.
Violation Message "Metal3 spacing < 0.3um (met3.2) "found 8972 Times.
Violation Message "Via1 width < 0.26um (via.1a + 2 * via.4a) "found 8 Times.
Violation Message "P-diff distance to N-tap must be < 15.0um (LU.3) "found 2720 Times.
Violation Message "Metal2 width < 0.14um (met2.1) "found 6 Times.
Violation Message "via2 spacing < 0.12um (via2.2 - 2 * via2.4) "found 440 Times.
Violation Message "HVI to HVI or LV nwell spacing < 0.7um (hvi.5) "found 154 Times.
Violation Message "N-diff distance to P-tap must be < 15.0um (LU.2) "found 2426 Times.
Total Magic DRC violations is 24867
----------------------------------------

LVS Summary:
Source: /openlane/designs/tt/runs/RUN_2021.11.05_21.51.38/results/lvs/top.lvs_parsed.gds.log
    net count difference = 34
    unmatched nets = 83
Total errors = 129
significantly reduced the LVS errors aligning the horizontal rails
the vertical power straps aren't regularly placed so I am looking for some help in the open lane channel, but yes it seems that You were right @User
@User Hi, I was replacing the macro and I founa sweet point where I got only 1 LVS violation and no DRC's. Would yo be so kind and give me some feedback how to debug this violation I have. The other thing is that even though I have only 1 error the visual inspection of the final design show that it seems to be unconnected to the VDD and VSS.
macro.png
t
@User: Well, first you would need to look at the LVS output file. Usually if there's just one error, then it's a simple short or an open, and the side-by-side comparison output should make that plain. Could also be a simple failure to reach a pin.
k
Hi, @User so my top.lvs.gds.log has like 5000, what would be the keywords ?
5000 lines
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Number of devices: 574                     |Number of devices: 574                     
Number of nets: 809                        |Number of nets: 809                        
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: top                             |Circuit 2: top                             

---------------------------------------------------------------------------------------
Net: _354_/X                               |Net: net43                                 
  sky130_fd_sc_hd__buf_2/A = 1             |  sky130_fd_sc_hd__buf_12/X = 1            
  sky130_fd_sc_hd__buf_12/X = 1            |  sky130_fd_sc_hd__buf_2/A = 1             
  SonarOnChip/wbs_adr_i[3] = 1             |                                           
  sky130_fd_sc_hd__buf_8/X = 1             |                                           
                                           |                                           
Net: soc1/VPWR                             |Net: \addr[3]                              
  SonarOnChip/VPWR = 1                     |  sky130_fd_sc_hd__buf_8/X = 1             
                                           |  SonarOnChip/wbs_adr_i[3] = 1             
                                           |                                           
Net: vccd1                                 |Net: vccd1                                 
  sky130_fd_sc_hd__decap_6/VPWR = 1        |  sky130_fd_sc_hd__decap_6/VPWR = 1        
  sky130_fd_sc_hd__decap_6/VPB = 1         |  sky130_fd_sc_hd__decap_6/VPB = 1         
  sky130_fd_sc_hd__decap_12/VPWR = 1       |  sky130_fd_sc_hd__decap_12/VPWR = 1       
  sky130_fd_sc_hd__decap_12/VPB = 1        |  sky130_fd_sc_hd__decap_12/VPB = 1        
  sky130_fd_sc_hd__decap_4/VPWR = 1        |  sky130_fd_sc_hd__decap_4/VPWR = 1        
  sky130_fd_sc_hd__decap_4/VPB = 1         |  sky130_fd_sc_hd__decap_4/VPB = 1         
  sky130_fd_sc_hd__decap_8/VPWR = 1        |  sky130_fd_sc_hd__decap_8/VPWR = 1        
  sky130_fd_sc_hd__decap_8/VPB = 1         |  sky130_fd_sc_hd__decap_8/VPB = 1         
  sky130_fd_sc_hd__conb_1/VPWR = 206       |  sky130_fd_sc_hd__conb_1/VPWR = 206       
  sky130_fd_sc_hd__inv_2/VPB = 41          |  sky130_fd_sc_hd__inv_2/VPB = 41          
  sky130_fd_sc_hd__inv_2/VPWR = 41         |  sky130_fd_sc_hd__inv_2/VPWR = 41         
  sky130_fd_sc_hd__decap_3/VPWR = 1        |  sky130_fd_sc_hd__decap_3/VPWR = 1        
  sky130_fd_sc_hd__decap_3/VPB = 1         |  sky130_fd_sc_hd__decap_3/VPB = 1         
  sky130_fd_sc_hd__and2_2/VPWR = 3         |  sky130_fd_sc_hd__and2_2/VPWR = 3         
  sky130_fd_sc_hd__and2_2/VPB = 3          |  sky130_fd_sc_hd__and2_2/VPB = 3          
  sky130_fd_sc_hd__or2_1/VPB = 11          |  sky130_fd_sc_hd__or2_1/VPB = 11          
  sky130_fd_sc_hd__or2_1/VPWR = 11         |  sky130_fd_sc_hd__or2_1/VPWR = 11         
  sky130_fd_sc_hd__nor2_1/VPB = 15         |  sky130_fd_sc_hd__nor2_1/VPB = 15         
  sky130_fd_sc_hd__nor2_1/VPWR = 15        |  sky130_fd_sc_hd__nor2_1/VPWR = 15        
  sky130_fd_sc_hd__or3_1/VPWR = 4          |  sky130_fd_sc_hd__or3_1/VPWR = 4          
  sky130_fd_sc_hd__or3_1/VPB = 4           |  sky130_fd_sc_hd__or3_1/VPB = 4           
  sky130_fd_sc_hd__dfxtp_1/VPB = 39        |  sky130_fd_sc_hd__dfxtp_1/VPB = 39        
  sky130_fd_sc_hd__dfxtp_1/VPWR = 39       |  sky130_fd_sc_hd__dfxtp_1/VPWR = 39       
  sky130_fd_sc_hd__buf_2/VPWR = 36         |  sky130_fd_sc_hd__buf_2/VPWR = 36         
  sky130_fd_sc_hd__buf_2/VPB = 36          |  sky130_fd_sc_hd__buf_2/VPB = 36          
  sky130_fd_sc_hd__clkbuf_1/VPWR = 19      |  sky130_fd_sc_hd__clkbuf_1/VPWR = 19      
  sky130_fd_sc_hd__clkbuf_1/VPB = 19       |  sky130_fd_sc_hd__clkbuf_1/VPB = 19       
  sky130_fd_sc_hd__buf_1/VPWR = 8          |  sky130_fd_sc_hd__buf_1/VPWR = 8          
  sky130_fd_sc_hd__buf_1/VPB = 8           |  sky130_fd_sc_hd__buf_1/VPB = 8           
  sky130_fd_sc_hd__buf_4/VPWR = 7          |  sky130_fd_sc_hd__buf_4/VPWR = 7          
  sky130_fd_sc_hd__buf_4/VPB = 7           |  sky130_fd_sc_hd__buf_4/VPB = 7           
  sky130_fd_sc_hd__and4_1/VPWR = 3         |  sky130_fd_sc_hd__and4_1/VPWR = 3         
  sky130_fd_sc_hd__and4_1/VPB = 3          |  sky130_fd_sc_hd__and4_1/VPB = 3          
  sky130_fd_sc_hd__o221a_1/VPB = 24        |  sky130_fd_sc_hd__o221a_1/VPB = 24        
  sky130_fd_sc_hd__o221a_1/VPWR = 24       |  sky130_fd_sc_hd__o221a_1/VPWR = 24       
  sky130_fd_sc_hd__mux2_8/VPWR = 8         |  sky130_fd_sc_hd__mux2_8/VPWR = 8         
  sky130_fd_sc_hd__mux2_8/VPB = 8          |  sky130_fd_sc_hd__mux2_8/VPB = 8          
  sky130_fd_sc_hd__and2_1/VPWR = 5         |  sky130_fd_sc_hd__and2_1/VPWR = 5         
  sky130_fd_sc_hd__and2_1/VPB = 5          |  sky130_fd_sc_hd__and2_1/VPB = 5          
  sky130_fd_sc_hd__o22a_1/VPB = 6          |  sky130_fd_sc_hd__o22a_1/VPB = 6          
  sky130_fd_sc_hd__o22a_1/VPWR = 6         |  sky130_fd_sc_hd__o22a_1/VPWR = 6         
  sky130_fd_sc_hd__clkinv_2/VPB = 3        |  sky130_fd_sc_hd__clkinv_2/VPB = 3        
  sky130_fd_sc_hd__clkinv_2/VPWR = 3       |  sky130_fd_sc_hd__clkinv_2/VPWR = 3       
  sky130_fd_sc_hd__o311a_1/VPB = 2         |  sky130_fd_sc_hd__o311a_1/VPB = 2         
  sky130_fd_sc_hd__o311a_1/VPWR = 2        |  sky130_fd_sc_hd__o311a_1/VPWR = 2        
  sky130_fd_sc_hd__buf_12/VPWR = 22        |  sky130_fd_sc_hd__buf_12/VPWR = 22        
  sky130_fd_sc_hd__buf_12/VPB = 22         |  sky130_fd_sc_hd__buf_12/VPB = 22         
  sky130_fd_sc_hd__or4_4/VPB = 2           |  sky130_fd_sc_hd__or4_4/VPB = 2           
  sky130_fd_sc_hd__or4_4/VPWR = 2          |  sky130_fd_sc_hd__or4_4/VPWR = 2          
  sky130_fd_sc_hd__mux2_2/VPWR = 1         |  sky130_fd_sc_hd__mux2_2/VPWR = 1         
  sky130_fd_sc_hd__mux2_2/VPB = 1          |  sky130_fd_sc_hd__mux2_2/VPB = 1          
  sky130_fd_sc_hd__a31o_1/VPB = 2          |  sky130_fd_sc_hd__a31o_1/VPB = 2          
  sky130_fd_sc_hd__a31o_1/VPWR = 2         |  sky130_fd_sc_hd__a31o_1/VPWR = 2         
  sky130_fd_sc_hd__o211a_1/VPB = 6         |  sky130_fd_sc_hd__o211a_1/VPB = 6         
  sky130_fd_sc_hd__o211a_1/VPWR = 6        |  sky130_fd_sc_hd__o211a_1/VPWR = 6        
  sky130_fd_sc_hd__or4b_1/VPWR = 1         |  sky130_fd_sc_hd__or4b_1/VPWR = 1         
  sky130_fd_sc_hd__or4b_1/VPB = 1          |  sky130_fd_sc_hd__or4b_1/VPB = 1          
  sky130_fd_sc_hd__nand2_8/VPB = 1         |  sky130_fd_sc_hd__nand2_8/VPB = 1         
  sky130_fd_sc_hd__nand2_8/VPWR = 1        |  sky130_fd_sc_hd__nand2_8/VPWR = 1        
  sky130_fd_sc_hd__nand2_4/VPB = 1         |  sky130_fd_sc_hd__nand2_4/VPB = 1         
  sky130_fd_sc_hd__nand2_4/VPWR = 1        |  sky130_fd_sc_hd__nand2_4/VPWR = 1        
  sky130_fd_sc_hd__a211oi_1/VPWR = 3       |  sky130_fd_sc_hd__a211oi_1/VPWR = 3       
  sky130_fd_sc_hd__a211oi_1/VPB = 3        |  sky130_fd_sc_hd__a211oi_1/VPB = 3        
  sky130_fd_sc_hd__clkbuf_2/VPWR = 21      |  sky130_fd_sc_hd__clkbuf_2/VPWR = 21      
  sky130_fd_sc_hd__clkbuf_2/VPB = 21       |  sky130_fd_sc_hd__clkbuf_2/VPB = 21       
  sky130_fd_sc_hd__dlymetal6s2s_1/VPWR = 1 |  sky130_fd_sc_hd__dlymetal6s2s_1/VPWR = 1 
  sky130_fd_sc_hd__dlymetal6s2s_1/VPB = 1  |  sky130_fd_sc_hd__dlymetal6s2s_1/VPB = 1  
  sky130_fd_sc_hd__a22o_1/VPWR = 2         |  sky130_fd_sc_hd__a22o_1/VPWR = 2         
  sky130_fd_sc_hd__a22o_1/VPB = 2          |  sky130_fd_sc_hd__a22o_1/VPB = 2          
  sky130_fd_sc_hd__a41o_1/VPWR = 2         |  sky130_fd_sc_hd__a41o_1/VPWR = 2         
  sky130_fd_sc_hd__a41o_1/VPB = 2          |  sky130_fd_sc_hd__a41o_1/VPB = 2          
  sky130_fd_sc_hd__nand2_1/VPB = 3         |  sky130_fd_sc_hd__nand2_1/VPB = 3         
  sky130_fd_sc_hd__nand2_1/VPWR = 3        |  sky130_fd_sc_hd__nand2_1/VPWR = 3        
  sky130_fd_sc_hd__inv_4/VPB = 5           |  sky130_fd_sc_hd__inv_4/VPB = 5           
  sky130_fd_sc_hd__inv_4/VPWR = 5          |  sky130_fd_sc_hd__inv_4/VPWR = 5          
  sky130_fd_sc_hd__and3_1/VPWR = 1         |  sky130_fd_sc_hd__and3_1/VPWR = 1         
  sky130_fd_sc_hd__and3_1/VPB = 1          |  sky130_fd_sc_hd__and3_1/VPB = 1          
  sky130_fd_sc_hd__buf_8/VPWR = 6          |  sky130_fd_sc_hd__buf_8/VPWR = 6          
  sky130_fd_sc_hd__buf_8/VPB = 6           |  sky130_fd_sc_hd__buf_8/VPB = 6           
  sky130_fd_sc_hd__buf_6/VPWR = 3          |  sky130_fd_sc_hd__buf_6/VPWR = 3          
  sky130_fd_sc_hd__buf_6/VPB = 3           |  sky130_fd_sc_hd__buf_6/VPB = 3           
  sky130_fd_sc_hd__mux2_4/VPB = 2          |  sky130_fd_sc_hd__mux2_4/VPB = 2          
  sky130_fd_sc_hd__mux2_4/VPWR = 2         |  sky130_fd_sc_hd__mux2_4/VPWR = 2         
  sky130_fd_sc_hd__inv_1/VPB = 1           |  sky130_fd_sc_hd__inv_1/VPB = 1           
  sky130_fd_sc_hd__inv_1/VPWR = 1          |  sky130_fd_sc_hd__inv_1/VPWR = 1          
  sky130_fd_sc_hd__clkbuf_16/VPB = 4       |  sky130_fd_sc_hd__clkbuf_16/VPB = 4       
  sky130_fd_sc_hd__clkbuf_16/VPWR = 4      |  sky130_fd_sc_hd__clkbuf_16/VPWR = 4      
  sky130_fd_sc_hd__clkbuf_8/VPB = 2        |  sky130_fd_sc_hd__clkbuf_8/VPB = 2        
  sky130_fd_sc_hd__clkbuf_8/VPWR = 2       |  sky130_fd_sc_hd__clkbuf_8/VPWR = 2       
  sky130_fd_sc_hd__and4b_1/VPWR = 1        |  sky130_fd_sc_hd__and4b_1/VPWR = 1        
  sky130_fd_sc_hd__and4b_1/VPB = 1         |  sky130_fd_sc_hd__and4b_1/VPB = 1         
  sky130_fd_sc_hd__o21a_1/VPB = 1          |  sky130_fd_sc_hd__o21a_1/VPB = 1          
  sky130_fd_sc_hd__o21a_1/VPWR = 1         |  sky130_fd_sc_hd__o21a_1/VPWR = 1         
  sky130_fd_sc_hd__clkdlybuf4s25_1/VPB = 1 |  sky130_fd_sc_hd__clkdlybuf4s25_1/VPB = 1 
  sky130_fd_sc_hd__clkdlybuf4s25_1/VPWR =  |  sky130_fd_sc_hd__clkdlybuf4s25_1/VPWR =  
  sky130_fd_sc_hd__a2bb2o_1/VPB = 1        |  sky130_fd_sc_hd__a2bb2o_1/VPB = 1        
  sky130_fd_sc_hd__a2bb2o_1/VPWR = 1       |  sky130_fd_sc_hd__a2bb2o_1/VPWR = 1       
  sky130_fd_sc_hd__a221o_1/VPWR = 3        |  sky130_fd_sc_hd__a221o_1/VPWR = 3        
  sky130_fd_sc_hd__a221o_1/VPB = 3         |  sky130_fd_sc_hd__a221o_1/VPB = 3         
  sky130_fd_sc_hd__nor2_8/VPB = 1          |  sky130_fd_sc_hd__nor2_8/VPB = 1          
  sky130_fd_sc_hd__nor2_8/VPWR = 1         |  sky130_fd_sc_hd__nor2_8/VPWR = 1         
  sky130_fd_sc_hd__inv_6/VPB = 1           |  sky130_fd_sc_hd__inv_6/VPB = 1           
  sky130_fd_sc_hd__inv_6/VPWR = 1          |  sky130_fd_sc_hd__inv_6/VPWR = 1          
  sky130_fd_sc_hd__dfxtp_2/VPB = 2         |  sky130_fd_sc_hd__dfxtp_2/VPB = 2         
  sky130_fd_sc_hd__dfxtp_2/VPWR = 2        |  sky130_fd_sc_hd__dfxtp_2/VPWR = 2        
  sky130_fd_sc_hd__dfxtp_4/VPWR = 1        |  sky130_fd_sc_hd__dfxtp_4/VPWR = 1        
  sky130_fd_sc_hd__dfxtp_4/VPB = 1         |  sky130_fd_sc_hd__dfxtp_4/VPB = 1         
  sky130_fd_sc_hd__or2_2/VPWR = 1          |  sky130_fd_sc_hd__or2_2/VPWR = 1          
  sky130_fd_sc_hd__or2_2/VPB = 1           |  sky130_fd_sc_hd__or2_2/VPB = 1           
                                           |  SonarOnChip/VPWR = 1                     
---------------------------------------------------------------------------------------
Netlists do not match.
Netlists do not match.
is the last entry on the right giving an issue ?
t
There are two issues here: (1) SonarOnChip/VPWR is not connected to vccd1 at the top level, and (2) the routing has created a short between nets "\addr[3] " and "net43".
k
Ok, I can figure out that the SonarOnChip/VPWR = 1 mean that it is only connected to itself and anything else, how do You deduce the second case
?
In fact there is a lot of gates not connected to the power rails I guess, ie. this one sky130_fd_sc_hd__or2_2/VPWR = 1
t
No, that's just a count of the pins of the same name. It means that there is one pin type sky130_fd_sc_hd__or2_2/VPWR connected to vccd1. . . which means that there is only one gate of type sky130_fd_sc_hd__or2_2 in the design.
This is a side-by-side comparison. If everything on the left side (the extracted layout netlist) has an exact match on the right side (the synthesized verilog gate-level netlist), then everything matches. I deduce the 2nd case is a short because the first net on the left side in the list has four connections, and on the right side those same four connections are split across the first two nets in the list.
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