Hi all I have a very similar issue to the one reported here

Question

Hi all I have a very similar issue to the one reported here <https github com The OpenROAD Project OpenLane issues 554> however I use sky130 fd sc hd cells In general it reports a lot of overlaps

Tim Edwards · Answer

Generally this doesn t happen unless you have macros in your design If you read the design into magic with macros abstracted it should show errors where routes are overlapping obstruction layers in the macro assuming that s the cause

Krzysztof Herman · Answer

Thank You for Your response < U016EM8L91B> yes I have macros instantiated I suppose that there exists some way to mitigate those overlaps

Tim Edwards · Answer

You would need to ask the Openlane developers whether this is an actual issue or if there is something you can do to your configuration This is something that would normally be handled automatically by the tools

Krzysztof Herman · Answer

ok Thank You

Krzysztof Herman · Answer

< U016EM8L91B> searching the logs I found this

Krzysztof Herman · Answer

``` WARNING Specifying a routing obstruction is now done using the coordinates WARNING of its bounding box instead of the now deprecated x y size x size y INFO Obstructions added over met5 0 0 2500 3200```

Krzysztof Herman · Answer

in fact the way I changed the flow to pass the flow was to extract spice from GDS not from LEF

Krzysztof Herman · Answer

``` INFO Running Magic Spice Export from GDS INFO current step index 41 INFO No Illegal overlaps detected during extraction INFO Running GDS LVS ```

Krzysztof Herman · Answer

It passes however it produces a lot of LVS mismatches

Krzysztof Herman · Answer

``` net count difference = 169881 unmatched nets = 1524 Total errors = 171475```

Krzysztof Herman · Answer

all on nets the device count matches

Krzysztof Herman · Answer

do You think it has something in common

Tim Edwards · Answer

I d have to see the whole LVS output file

Krzysztof Herman · Answer

Hi < U016EM8L91B> I will send it to You right now

Krzysztof Herman · Answer

top lvs gds log

Krzysztof Herman · Answer

I have limited the number of macros to 1 the orginal project instantiates 34

Krzysztof Herman · Answer

```Magic DRC Summary Source openlane designs tt runs RUN 2021 11 05 13 12 22 reports magic 43 magic drc Violation Message Via1 spacing lt 0 06um via 2 2 via 4a found 569 Times Violation Message N well spacing lt 1 27um nwell 2a found 94 Times Violation Message This layer can t abut or partially overlap between subcells found 8789 Times Violation Message Metal2 spacing lt 0 14um met2 2 found 6853 Times Violation Message Metal1 spacing lt 0 14um met1 2 found 46740 Times Violation Message N well width lt 0 84um nwell 1 found 32 Times Violation Message Min area of metal1 holes gt 0 14um^2 met1 7 found 10 Times Violation Message via2 width lt 0 28um via2 1a + 2 via2 4 found 117 Times Violation Message All nwells must contain metal connected N+ taps nwell 4 found 637 Times Violation Message Metal3 spacing lt 0 3um met3 2 found 1741 Times Violation Message Metal3 width lt 0 3um met3 1 found 3 Times Violation Message P diff distance to N tap must be lt 15 0um LU 3 found 2738 Times Violation Message Via1 width lt 0 26um via 1a + 2 via 4a found 858 Times Violation Message Metal2 width lt 0 14um met2 1 found 2 Times Violation Message via2 spacing lt 0 12um via2 2 2 via2 4 found 405 Times Violation Message HVI to HVI or LV nwell spacing lt 0 7um hvi 5 found 150 Times Violation Message N diff distance to P tap must be lt 15 0um LU 2 found 2642 Times Total Magic DRC violations is 72380 LVS Summary Source openlane designs tt runs RUN 2021 11 05 13 12 22 results lvs top lvs parsed gds log net count difference = 4535 unmatched nets = 103 Total errors = 4661 ```

Tim Edwards · Answer

< U01GLU3UDRD> There are several problems here the first is that there is a difference in the number of diode cells in top Possibly that would be due to one of the netlists not reflecting changes made to resolve antenna errors diode cells that are unused for tie downs get merged into a single device by parallel combination while all the diode cells used as tie downs are counted individually The bigger issue though is that the macro is totally screwed up in a way that I don t really understand If you can tarball up the two netlists I d like to take a look

Krzysztof Herman · Answer

ok let me do it

Krzysztof Herman · Answer

one question where does the OpenLane dumps the netlists

Krzysztof Herman · Answer

I can see the ext files and the respective gds and lef

Krzysztof Herman · Answer

```puts Reading spice netlist file home icarosix asictoolchain OpenLane pdks sky130A libs ref sky130 fd sc hd spice sky130 fd sc hd spice readnet spice home icarosix asictoolchain OpenLane pdks sky130A libs ref sky130 fd sc hd spice sky130 fd sc hd spice 1 lvs openlane designs tt runs RUN 2021 11 05 13 12 22 results magic top gds spice top openlane designs tt runs RUN 2021 11 05 13 12 22 results lvs top lvs powered v top home icarosix asictoolchain OpenLane pdks sky130A libs tech netgen sky130A setup tcl openlane designs tt runs RUN 2021 11 05 13 12 22 results lvs top lvs gds log json```

Krzysztof Herman · Answer

top lvs powered v

Krzysztof Herman · Answer

so here is the schematic

Krzysztof Herman · Answer

do You need the gds as well

Krzysztof Herman · Answer

As for the macro it passes LVS and DRC without issues

Krzysztof Herman · Answer

```Magic DRC Summary Source openlane designs SSCS SoC runs RUN 2021 11 02 17 19 14 reports magic 36 magic drc Total Magic DRC violations is 0 LVS Summary Source openlane designs SSCS SoC runs RUN 2021 11 02 17 19 14 results lvs SonarOnChip lvs parsed lef log LVS reports no net device pin or property mismatches Total errors = 0 Antenna Summary Source openlane designs SSCS SoC runs RUN 2021 11 02 17 19 14 reports routing 38 antenna rpt Number of pins violated 8 Number of nets violated 8```

Krzysztof Herman · Answer

except the antenna violations

Tim Edwards · Answer

It could be an issue with the verilog parser in netgen Can you post the SPICE netlist from the layout that it is being compared against better than the GDS since then I d have to go to the trouble of extracting it

Krzysztof Herman · Answer

ok the question is where the OpenLane dumps it

Krzysztof Herman · Answer

top gds spice

Tim Edwards · Answer

I think the verilog parser in netgen is not handling the net bundles on the SonarOnChip macro inputs properly It is supposed to so hopefully it is just some minor bug I can track down At any rate the main issue here seems to be a netgen parser error

Krzysztof Herman · Answer

ok hope You are right

Krzysztof Herman · Answer

Thank You

Tim Edwards · Answer

Thanks for providing the example files

Krzysztof Herman · Answer

What about the prechecks on the efabless platform will it pass it

Tim Edwards · Answer

It should the precheck does not do LVS and this issue is restricted to netgen as far as I can tell

Krzysztof Herman · Answer

ok soon I will have information about that so I will share

Krzysztof Herman · Answer

Thank You once more BTW I am very impressed by Your contribution into the open circuit design keep going

Tim Edwards · Answer

Oops wrong column The problem is in the layout netlist not the verilog netlist The layout netlist has somehow managed to promote all subcircuit pins of SonarOnChip to the top level of SonarOnChip That looks more like something that could possibly have been caused by a recent commit to magic What version of magic are you using and can you please provide the GDS as you originally offered

Krzysztof Herman · Answer

let me check the version

Krzysztof Herman · Answer

8 3 216

Krzysztof Herman · Answer

yes of course I can share the GDS

Krzysztof Herman · Answer

SonarOnChip zip

Krzysztof Herman · Answer

top zip

Krzysztof Herman · Answer

SonarOnChip is a gds of the macro instantiated within the top gds

Tim Edwards · Answer

Oh crud I broke magic

Tim Edwards · Answer

Looks like 8 3 214 broke it Try using 8 3 213 while I desperately try to fix this

Krzysztof Herman · Answer

ok lest give it a try

Krzysztof Herman · Answer

< U016EM8L91B> in fact the magic version used by the flow is the one from the docker image

Krzysztof Herman · Answer

8 3 209

Tim Edwards · Answer

< U01GLU3UDRD> Okay what I found was this The problem is in the layout it is not an issue with either magic or netgen If you look closely at the layout you will see that the SonarOnChip macro is shifted such that the metal1 power rails drawn over the whole layout at the top level are misaligned with the power rails in the standard cells in SonarOnChip and so power and ground are shorted and colliding with thousands of internal nets So the clue is that in the top spice file the definition for SonarOnChip added many extra nets as ports and the call to SonarOnChip in top connected all those ports to ground indicating a massive number of shorts between the cell s internal nets and the top level cell s ground Now I am not sure what causes the macro to be shifted but unless it can be shown that magic is mishandling an offset between the LEF and GDS of the macro which is a possibility then it should be treated as an error in Openlane If you would like me to double check the possibility of an offset issue please post the LEF file of SonarOnChip

Krzysztof Herman · Answer

< U016EM8L91B> cool that is a good information for You I hope Here goes the LEF file

Krzysztof Herman · Answer

SonarOnChip lef

Krzysztof Herman · Answer

In fact what I am doing is placing the macro manually using macro cfg file

Krzysztof Herman · Answer

soc1 90 20 N

Krzysztof Herman · Answer

Do You know how to place is in a correct aligned way

Krzysztof Herman · Answer

The other thing is that when I build the macro I got this

Krzysztof Herman · Answer

``` WARNING Current core area is too small for a power grid WARNING THE POWER GRID WILL BE MINIMIZED ```

Tim Edwards · Answer

This is an openlane message presumably from the power distribution network generator so I don t know what the implications are For that and also for the alignment issue I suggest you contact the openlane developers

Krzysztof Herman · Answer

ok thank You

Krzysztof Herman · Answer

```Magic DRC Summary Source openlane designs tt runs RUN 2021 11 05 21 51 38 reports magic 43 magic drc Violation Message Via1 spacing lt 0 06um via 2 2 via 4a found 5 Times Violation Message N well spacing lt 1 27um nwell 2a found 96 Times Violation Message This layer can t abut or partially overlap between subcells found 6677 Times Violation Message Metal2 spacing lt 0 14um met2 2 found 2707 Times Violation Message N well width lt 0 84um nwell 1 found 28 Times Violation Message All nwells must contain metal connected N+ taps nwell 4 found 628 Times Violation Message Metal3 spacing lt 0 3um met3 2 found 8972 Times Violation Message Via1 width lt 0 26um via 1a + 2 via 4a found 8 Times Violation Message P diff distance to N tap must be lt 15 0um LU 3 found 2720 Times Violation Message Metal2 width lt 0 14um met2 1 found 6 Times Violation Message via2 spacing lt 0 12um via2 2 2 via2 4 found 440 Times Violation Message HVI to HVI or LV nwell spacing lt 0 7um hvi 5 found 154 Times Violation Message N diff distance to P tap must be lt 15 0um LU 2 found 2426 Times Total Magic DRC violations is 24867 LVS Summary Source openlane designs tt runs RUN 2021 11 05 21 51 38 results lvs top lvs parsed gds log net count difference = 34 unmatched nets = 83 Total errors = 129```

Krzysztof Herman · Answer

significantly reduced the LVS errors aligning the horizontal rails

Krzysztof Herman · Answer

the vertical power straps aren t regularly placed so I am looking for some help in the open lane channel but yes it seems that You were right < U016EM8L91B>

Krzysztof Herman · Answer

< U016EM8L91B> Hi I was replacing the macro and I founa sweet point where I got only 1 LVS violation and no DRC s Would yo be so kind and give me some feedback how to debug this violation I have The other thing is that even though I have only 1 error the visual inspection of the final design show that it seems to be unconnected to the VDD and VSS

Krzysztof Herman · Answer

macro png

Tim Edwards · Answer

< U01GLU3UDRD> Well first you would need to look at the LVS output file Usually if there s just one error then it s a simple short or an open and the side by side comparison output should make that plain Could also be a simple failure to reach a pin

Krzysztof Herman · Answer

Hi < U016EM8L91B> so my top lvs gds log has like 5000 what would be the keywords

Krzysztof Herman · Answer

5000 lines

Krzysztof Herman · Answer

```Number of devices 574 |Number of devices 574 Number of nets 809 |Number of nets 809 NET mismatches Class fragments follow with fanout counts Circuit 1 top |Circuit 2 top Net 354 X |Net net43 sky130 fd sc hd buf 2 A = 1 | sky130 fd sc hd buf 12 X = 1 sky130 fd sc hd buf 12 X = 1 | sky130 fd sc hd buf 2 A = 1 SonarOnChip wbs adr i 3 = 1 | sky130 fd sc hd buf 8 X = 1 | | Net soc1 VPWR |Net addr 3 SonarOnChip VPWR = 1 | sky130 fd sc hd buf 8 X = 1 | SonarOnChip wbs adr i 3 = 1 | Net vccd1 |Net vccd1 sky130 fd sc hd decap 6 VPWR = 1 | sky130 fd sc hd decap 6 VPWR = 1 sky130 fd sc hd decap 6 VPB = 1 | sky130 fd sc hd decap 6 VPB = 1 sky130 fd sc hd decap 12 VPWR = 1 | sky130 fd sc hd decap 12 VPWR = 1 sky130 fd sc hd decap 12 VPB = 1 | sky130 fd sc hd decap 12 VPB = 1 sky130 fd sc hd decap 4 VPWR = 1 | sky130 fd sc hd decap 4 VPWR = 1 sky130 fd sc hd decap 4 VPB = 1 | sky130 fd sc hd decap 4 VPB = 1 sky130 fd sc hd decap 8 VPWR = 1 | sky130 fd sc hd decap 8 VPWR = 1 sky130 fd sc hd decap 8 VPB = 1 | sky130 fd sc hd decap 8 VPB = 1 sky130 fd sc hd conb 1 VPWR = 206 | sky130 fd sc hd conb 1 VPWR = 206 sky130 fd sc hd inv 2 VPB = 41 | sky130 fd sc hd inv 2 VPB = 41 sky130 fd sc hd inv 2 VPWR = 41 | sky130 fd sc hd inv 2 VPWR = 41 sky130 fd sc hd decap 3 VPWR = 1 | sky130 fd sc hd decap 3 VPWR = 1 sky130 fd sc hd decap 3 VPB = 1 | sky130 fd sc hd decap 3 VPB = 1 sky130 fd sc hd and2 2 VPWR = 3 | sky130 fd sc hd and2 2 VPWR = 3 sky130 fd sc hd and2 2 VPB = 3 | sky130 fd sc hd and2 2 VPB = 3 sky130 fd sc hd or2 1 VPB = 11 | sky130 fd sc hd or2 1 VPB = 11 sky130 fd sc hd or2 1 VPWR = 11 | sky130 fd sc hd or2 1 VPWR = 11 sky130 fd sc hd nor2 1 VPB = 15 | sky130 fd sc hd nor2 1 VPB = 15 sky130 fd sc hd nor2 1 VPWR = 15 | sky130 fd sc hd nor2 1 VPWR = 15 sky130 fd sc hd or3 1 VPWR = 4 | sky130 fd sc hd or3 1 VPWR = 4 sky130 fd sc hd or3 1 VPB = 4 | sky130 fd sc hd or3 1 VPB = 4 sky130 fd sc hd dfxtp 1 VPB = 39 | sky130 fd sc hd dfxtp 1 VPB = 39 sky130 fd sc hd dfxtp 1 VPWR = 39 | sky130 fd sc hd dfxtp 1 VPWR = 39 sky130 fd sc hd buf 2 VPWR = 36 | sky130 fd sc hd buf 2 VPWR = 36 sky130 fd sc hd buf 2 VPB = 36 | sky130 fd sc hd buf 2 VPB = 36 sky130 fd sc hd clkbuf 1 VPWR = 19 | sky130 fd sc hd clkbuf 1 VPWR = 19 sky130 fd sc hd clkbuf 1 VPB = 19 | sky130 fd sc hd clkbuf 1 VPB = 19 sky130 fd sc hd buf 1 VPWR = 8 | sky130 fd sc hd buf 1 VPWR = 8 sky130 fd sc hd buf 1 VPB = 8 | sky130 fd sc hd buf 1 VPB = 8 sky130 fd sc hd buf 4 VPWR = 7 | sky130 fd sc hd buf 4 VPWR = 7 sky130 fd sc hd buf 4 VPB = 7 | sky130 fd sc hd buf 4 VPB = 7 sky130 fd sc hd and4 1 VPWR = 3 | sky130 fd sc hd and4 1 VPWR = 3 sky130 fd sc hd and4 1 VPB = 3 | sky130 fd sc hd and4 1 VPB = 3 sky130 fd sc hd o221a 1 VPB = 24 | sky130 fd sc hd o221a 1 VPB = 24 sky130 fd sc hd o221a 1 VPWR = 24 | sky130 fd sc hd o221a 1 VPWR = 24 sky130 fd sc hd mux2 8 VPWR = 8 | sky130 fd sc hd mux2 8 VPWR = 8 sky130 fd sc hd mux2 8 VPB = 8 | sky130 fd sc hd mux2 8 VPB = 8 sky130 fd sc hd and2 1 VPWR = 5 | sky130 fd sc hd and2 1 VPWR = 5 sky130 fd sc hd and2 1 VPB = 5 | sky130 fd sc hd and2 1 VPB = 5 sky130 fd sc hd o22a 1 VPB = 6 | sky130 fd sc hd o22a 1 VPB = 6 sky130 fd sc hd o22a 1 VPWR = 6 | sky130 fd sc hd o22a 1 VPWR = 6 sky130 fd sc hd clkinv 2 VPB = 3 | sky130 fd sc hd clkinv 2 VPB = 3 sky130 fd sc hd clkinv 2 VPWR = 3 | sky130 fd sc hd clkinv 2 VPWR = 3 sky130 fd sc hd o311a 1 VPB = 2 | sky130 fd sc hd o311a 1 VPB = 2 sky130 fd sc hd o311a 1 VPWR = 2 | sky130 fd sc hd o311a 1 VPWR = 2 sky130 fd sc hd buf 12 VPWR = 22 | sky130 fd sc hd buf 12 VPWR = 22 sky130 fd sc hd buf 12 VPB = 22 | sky130 fd sc hd buf 12 VPB = 22 sky130 fd sc hd or4 4 VPB = 2 | sky130 fd sc hd or4 4 VPB = 2 sky130 fd sc hd or4 4 VPWR = 2 | sky130 fd sc hd or4 4 VPWR = 2 sky130 fd sc hd mux2 2 VPWR = 1 | sky130 fd sc hd mux2 2 VPWR = 1 sky130 fd sc hd mux2 2 VPB = 1 | sky130 fd sc hd mux2 2 VPB = 1 sky130 fd sc hd a31o 1 VPB = 2 | sky130 fd sc hd a31o 1 VPB = 2 sky130 fd sc hd a31o 1 VPWR = 2 | sky130 fd sc hd a31o 1 VPWR = 2 sky130 fd sc hd o211a 1 VPB = 6 | sky130 fd sc hd o211a 1 VPB = 6 sky130 fd sc hd o211a 1 VPWR = 6 | sky130 fd sc hd o211a 1 VPWR = 6 sky130 fd sc hd or4b 1 VPWR = 1 | sky130 fd sc hd or4b 1 VPWR = 1 sky130 fd sc hd or4b 1 VPB = 1 | sky130 fd sc hd or4b 1 VPB = 1 sky130 fd sc hd nand2 8 VPB = 1 | sky130 fd sc hd nand2 8 VPB = 1 sky130 fd sc hd nand2 8 VPWR = 1 | sky130 fd sc hd nand2 8 VPWR = 1 sky130 fd sc hd nand2 4 VPB = 1 | sky130 fd sc hd nand2 4 VPB = 1 sky130 fd sc hd nand2 4 VPWR = 1 | sky130 fd sc hd nand2 4 VPWR = 1 sky130 fd sc hd a211oi 1 VPWR = 3 | sky130 fd sc hd a211oi 1 VPWR = 3 sky130 fd sc hd a211oi 1 VPB = 3 | sky130 fd sc hd a211oi 1 VPB = 3 sky130 fd sc hd clkbuf 2 VPWR = 21 | sky130 fd sc hd clkbuf 2 VPWR = 21 sky130 fd sc hd clkbuf 2 VPB = 21 | sky130 fd sc hd clkbuf 2 VPB = 21 sky130 fd sc hd dlymetal6s2s 1 VPWR = 1 | sky130 fd sc hd dlymetal6s2s 1 VPWR = 1 sky130 fd sc hd dlymetal6s2s 1 VPB = 1 | sky130 fd sc hd dlymetal6s2s 1 VPB = 1 sky130 fd sc hd a22o 1 VPWR = 2 | sky130 fd sc hd a22o 1 VPWR = 2 sky130 fd sc hd a22o 1 VPB = 2 | sky130 fd sc hd a22o 1 VPB = 2 sky130 fd sc hd a41o 1 VPWR = 2 | sky130 fd sc hd a41o 1 VPWR = 2 sky130 fd sc hd a41o 1 VPB = 2 | sky130 fd sc hd a41o 1 VPB = 2 sky130 fd sc hd nand2 1 VPB = 3 | sky130 fd sc hd nand2 1 VPB = 3 sky130 fd sc hd nand2 1 VPWR = 3 | sky130 fd sc hd nand2 1 VPWR = 3 sky130 fd sc hd inv 4 VPB = 5 | sky130 fd sc hd inv 4 VPB = 5 sky130 fd sc hd inv 4 VPWR = 5 | sky130 fd sc hd inv 4 VPWR = 5 sky130 fd sc hd and3 1 VPWR = 1 | sky130 fd sc hd and3 1 VPWR = 1 sky130 fd sc hd and3 1 VPB = 1 | sky130 fd sc hd and3 1 VPB = 1 sky130 fd sc hd buf 8 VPWR = 6 | sky130 fd sc hd buf 8 VPWR = 6 sky130 fd sc hd buf 8 VPB = 6 | sky130 fd sc hd buf 8 VPB = 6 sky130 fd sc hd buf 6 VPWR = 3 | sky130 fd sc hd buf 6 VPWR = 3 sky130 fd sc hd buf 6 VPB = 3 | sky130 fd sc hd buf 6 VPB = 3 sky130 fd sc hd mux2 4 VPB = 2 | sky130 fd sc hd mux2 4 VPB = 2 sky130 fd sc hd mux2 4 VPWR = 2 | sky130 fd sc hd mux2 4 VPWR = 2 sky130 fd sc hd inv 1 VPB = 1 | sky130 fd sc hd inv 1 VPB = 1 sky130 fd sc hd inv 1 VPWR = 1 | sky130 fd sc hd inv 1 VPWR = 1 sky130 fd sc hd clkbuf 16 VPB = 4 | sky130 fd sc hd clkbuf 16 VPB = 4 sky130 fd sc hd clkbuf 16 VPWR = 4 | sky130 fd sc hd clkbuf 16 VPWR = 4 sky130 fd sc hd clkbuf 8 VPB = 2 | sky130 fd sc hd clkbuf 8 VPB = 2 sky130 fd sc hd clkbuf 8 VPWR = 2 | sky130 fd sc hd clkbuf 8 VPWR = 2 sky130 fd sc hd and4b 1 VPWR = 1 | sky130 fd sc hd and4b 1 VPWR = 1 sky130 fd sc hd and4b 1 VPB = 1 | sky130 fd sc hd and4b 1 VPB = 1 sky130 fd sc hd o21a 1 VPB = 1 | sky130 fd sc hd o21a 1 VPB = 1 sky130 fd sc hd o21a 1 VPWR = 1 | sky130 fd sc hd o21a 1 VPWR = 1 sky130 fd sc hd clkdlybuf4s25 1 VPB = 1 | sky130 fd sc hd clkdlybuf4s25 1 VPB = 1 sky130 fd sc hd clkdlybuf4s25 1 VPWR = | sky130 fd sc hd clkdlybuf4s25 1 VPWR = sky130 fd sc hd a2bb2o 1 VPB = 1 | sky130 fd sc hd a2bb2o 1 VPB = 1 sky130 fd sc hd a2bb2o 1 VPWR = 1 | sky130 fd sc hd a2bb2o 1 VPWR = 1 sky130 fd sc hd a221o 1 VPWR = 3 | sky130 fd sc hd a221o 1 VPWR = 3 sky130 fd sc hd a221o 1 VPB = 3 | sky130 fd sc hd a221o 1 VPB = 3 sky130 fd sc hd nor2 8 VPB = 1 | sky130 fd sc hd nor2 8 VPB = 1 sky130 fd sc hd nor2 8 VPWR = 1 | sky130 fd sc hd nor2 8 VPWR = 1 sky130 fd sc hd inv 6 VPB = 1 | sky130 fd sc hd inv 6 VPB = 1 sky130 fd sc hd inv 6 VPWR = 1 | sky130 fd sc hd inv 6 VPWR = 1 sky130 fd sc hd dfxtp 2 VPB = 2 | sky130 fd sc hd dfxtp 2 VPB = 2 sky130 fd sc hd dfxtp 2 VPWR = 2 | sky130 fd sc hd dfxtp 2 VPWR = 2 sky130 fd sc hd dfxtp 4 VPWR = 1 | sky130 fd sc hd dfxtp 4 VPWR = 1 sky130 fd sc hd dfxtp 4 VPB = 1 | sky130 fd sc hd dfxtp 4 VPB = 1 sky130 fd sc hd or2 2 VPWR = 1 | sky130 fd sc hd or2 2 VPWR = 1 sky130 fd sc hd or2 2 VPB = 1 | sky130 fd sc hd or2 2 VPB = 1 | SonarOnChip VPWR = 1 Netlists do not match Netlists do not match ```

Krzysztof Herman · Answer

is the last entry on the right giving an issue

Tim Edwards · Answer

There are two issues here 1 SonarOnChip VPWR is not connected to vccd1 at the top level and 2 the routing has created a short between nets addr 3 and net43

Krzysztof Herman · Answer

Ok I can figure out that the SonarOnChip VPWR = 1 mean that it is only connected to itself and anything else how do You deduce the second case

Krzysztof Herman · Answer

In fact there is a lot of gates not connected to the power rails I guess ie this one sky130 fd sc hd or2 2 VPWR = 1

Tim Edwards · Answer

No that s just a count of the pins of the same name It means that there is one pin type sky130 fd sc hd or2 2 VPWR connected to vccd1 which means that there is only one gate of type sky130 fd sc hd or2 2 in the design

Tim Edwards · Answer

This is a side by side comparison If everything on the left side the extracted layout netlist has an exact match on the right side the synthesized verilog gate level netlist then everything matches I deduce the 2nd case is a short because the first net on the left side in the list has four connections and on the right side those same four connections are split across the first two nets in the list