All previous steps are completed successfully but I m gettin

Question

All previous steps are completed successfully but I m getting error at routing can anyone please guide me about this Attached are the error and config tcl screenshots

Hadir Khan · Answer

What is your caravel lite commit

Vijayan Krishnan · Answer

share runs run1 openroad issue reproducible tar file

Vijayan Krishnan · Answer

seems you re running estimate parasitics global routing without running global route

Junaid amjad · Answer

< Vijayan Krishnan> Sir kindly check it

Vijayan Krishnan · Answer

file format not support what you shared share as zip or tar file

Junaid amjad · Answer

< Vijayan Krishnan> Sorry for inconvenience

Junaid amjad · Answer

This file is fine or not < Vijayan Krishnan>

Vijayan Krishnan · Answer

able to get same issue

Junaid amjad · Answer

< Vijayan Krishnan> Check now

Junaid amjad · Answer

< Hadir Khan> right now I m just running the openlane flow not caravel flow

Vijayan Krishnan · Answer

am able to reproduce your issue at my end

Vijayan Krishnan · Answer

working on that

Vijayan Krishnan · Answer

can you share your config tcl so it will be easy to find what are additional settings you added

Junaid amjad · Answer

BTW I have attached a screenshot of config tcl < Vijayan Krishnan> But let me send you the complete file as well

Junaid amjad · Answer

I really appreciate your time < Vijayan Krishnan>

Junaid amjad · Answer

I m stuck at routing for like now two days

Junaid amjad · Answer

I m trying different variables at different steps but it s not working

Junaid amjad · Answer

< Vijayan Krishnan>

Vijayan Krishnan · Answer

set env GLB RESIZER TIMING OPTIMIZATIONS 0 add this in config tcl and try once

Junaid amjad · Answer

Now getting this error at routing < Vijayan Krishnan>

Junaid amjad · Answer

Vijayan Krishnan · Answer

``` User config set env DESIGN NAME main Change if needed set env VERILOG FILES glob $ env DESIGN DIR src v Fill this set env CLOCK PERIOD 100 set env CLOCK PORT clk set env SYNTH READ BLACKBOX LIB 1 set env SYNTH USE PG PINS DEFINES USE POWER PINS set env FP SIZING absolute set env DIE AREA 0 0 2920 3520 set env RUN CVC 0 set filename $ env DESIGN DIR $ env PDK $ env STD CELL LIBRARY config tcl if file exists $filename == 1 source $filename ```

Junaid amjad · Answer

< Vijayan Krishnan> If you have time can you take a look at above my repo and guide me about it like which variables should I use to run the flow

Vijayan Krishnan · Answer

try this config tcl once and let me know

Vijayan Krishnan · Answer

which openlane version are you using

Junaid amjad · Answer

I just installed it a week ago tbh I don t know which version is this

Junaid amjad · Answer

but I think this must be the latest bcz I installed just a week ago

Vijayan Krishnan · Answer

in the repo link which is your top design

Junaid amjad · Answer

top level v

Vijayan Krishnan · Answer

i m updating my openlane repo now Update you once i check it

Junaid amjad · Answer

In instruction memory v I read machine code from mem file so if you will not add that file it will give error

Junaid amjad · Answer

let me send you instruction memory v file with some hard code machine codes

Junaid amjad · Answer

< Vijayan Krishnan> you can use this

Vijayan Krishnan · Answer

+1

Junaid amjad · Answer

getting same estimating parasitic error with your config tcl as well

Vijayan Krishnan · Answer

11 Executing Verilog 2005 frontend openlane designs risc32 scp src Controller v openlane designs risc32 scp src Controller sv2v v 12 ERROR syntax error unexpected TOK CHECKER expecting TOK ID or ERROR during executing yosys c openlane scripts yosys synth tcl l openlane designs risc32 scp runs 1strun logs synthesis 1 synthesis log | amp tee gt amp stdout

Vijayan Krishnan · Answer

facing issue at synthesis itself

Junaid amjad · Answer

let me send you updated file

Junaid amjad · Answer

use this file although it does not have any syntax error earlier as well but I don t know why it gave this syntax error

Junaid amjad · Answer

but with this file you will not get this syntax error < Vijayan Krishnan>

Vijayan Krishnan · Answer

I m not able to get same error with the repo ``` config openlane scripts openroad pdn cfg tcl ERROR PDN 0085 Pitch 3 6799999999999997 specified for layer met4 is less than 2 x width + spacing width=3 0 spacing=1 84 Error pdn cfg tcl 39 PDN 0085```

Junaid amjad · Answer

so noe what is this error

Junaid amjad · Answer

and can you share your config tcl

Vijayan Krishnan · Answer

Change if needed set env VERILOG FILES glob $ env DESIGN DIR src v Fill this set env CLOCK PERIOD 10 0 set env CLOCK PORT clk set filename $ env DESIGN DIR $ env PDK $ env STD CELL LIBRARY config tcl if file exists $filename == 1 source $filename set env SYNTH READ BLACKBOX LIB 1 set env SYNTH USE PG PINS DEFINES USE POWER PINS set env FP SIZING absolute set env DIE AREA 0 0 2920 3520 set env RUN CVC 0 set env FP PDN CORE RING 1 set env FP PDN CORE RING VWIDTH 3 set env FP PDN CORE RING HWIDTH $ env FP PDN CORE RING VWIDTH set env FP PDN CORE RING VOFFSET 14 set env FP PDN CORE RING HOFFSET $ env FP PDN CORE RING VOFFSET set env FP PDN CORE RING VSPACING 1 7 set env FP PDN CORE RING HSPACING $ env FP PDN CORE RING VSPACING set env FP PDN VWIDTH 3 set env FP PDN HWIDTH 3 set env FP PDN VOFFSET 5 set env FP PDN HOFFSET $ env FP PDN VOFFSET set env FP PDN VPITCH 180 set env FP PDN HPITCH $ env FP PDN VPITCH set env FP PDN VSPACING expr 5 $ env FP PDN CORE RING VWIDTH set env FP PDN HSPACING expr 5 $ env FP PDN CORE RING HWIDTH set env VDD NETS list vccd1 vccd2 vdda1 vdda2 set env GND NETS list vssd1 vssd2 vssa1 vssa2 set env SYNTH USE PG PINS DEFINES USE POWER PINS set env FP PDN CHECK NODES 0

Vijayan Krishnan · Answer

seems i m running wrong repo of verilog source code zero instance found from the top file you gave Please provide right src zip file

Junaid amjad · Answer

source repo is upto date

Junaid amjad · Answer

there might be some other issues

Vijayan Krishnan · Answer

``` 30 Printing statistics === risc32 scp === Number of wires 2 Number of wire bits 2 Number of public wires 2 Number of public wire bits 2 Number of memories 0 Number of memory bits 0 Number of processes 0 Number of cells 0```

Vijayan Krishnan · Answer

no cells found from your verilog code I just changed top module name main to risc32 scp

Junaid amjad · Answer

so what does this mean

Junaid amjad · Answer

like my verilog files are wrong

Vijayan Krishnan · Answer

can you share your runs logs synthesis 1 synthesis log

Junaid amjad · Answer

1 synthesis log

Vijayan Krishnan · Answer

same in your end aslo ``` Number of wires 2 Number of wire bits 2 Number of public wires 2 Number of public wire bits 2 Number of memories 0 Number of memory bits 0 Number of processes 0 Number of cells 0```

Junaid amjad · Answer

it is tested design through vivado

Junaid amjad · Answer

i have syhthesised it using vivado and it s fine

Junaid amjad · Answer

what do you think issue might be

Junaid amjad · Answer

bcz it s a tested design

Junaid amjad · Answer

ok so what can you infer through errors which you are getting during flow

Junaid amjad · Answer

all files are completely in verilog

Vijayan Krishnan · Answer

using the repo source file zero instance used so tool not doing any placement

Vijayan Krishnan · Answer

first time am seeing this error Raise github issue some one will guide you

Junaid amjad · Answer

BTW you are purely backend engineer

Vijayan Krishnan · Answer

yes

Junaid amjad · Answer

you have also happened to work on cadence tools

Junaid amjad · Answer

can you give me your email id bcz I have couple of other desighns as well like 5 stage pipeline and I m also implementing some peripherals as well so will you be willing to help me with them if I need any

Vijayan Krishnan · Answer

you can DM here itself or raise github other experts will help you

Junaid amjad · Answer

ok can you share some backend resources for beginners

Junaid amjad · Answer

like there is almost nothing available when it comes to backend

Vijayan Krishnan · Answer

<https github com The OpenROAD Project OpenROAD tree master src> refer each tool READEME md here

Vijayan Krishnan · Answer

Junaid amjad · Answer

ok I really appreciate your time

Junaid amjad · Answer

thank you so much

Junaid amjad · Answer

I try to find out like what is the issue in verilog files

Vijayan Krishnan · Answer

< Junaid amjad> I checked with Frontend team The verilog looks ok But during yosys synthesis top level unconnected signals removed by OPT CLEAN ```15 5 Executing OPT CLEAN pass remove unused cells and wires Finding unused cells or wires in module main Removed 1010 unused cells and 1736 unused wires lt suppressed ~1104 debug messages gt ``` Need to find option to skip this

Junaid amjad · Answer

< Vijayan Krishnan> So what do I need to do now

Junaid amjad · Answer

like you are saying that my top level connections are wrong or what

Vijayan Krishnan · Answer

<https github com The OpenROAD Project OpenLane issues 834> tag yourself here and follow up

Vijayan Krishnan · Answer

< Junaid amjad> can you tag yourself in the above github issue Answer the experts question so it will be resolved else it will be closed

donn · Answer

< Junaid amjad>

Junaid amjad · Answer

<https github com donn| donn> yes you are right design does not has any output because it s very basic level single cycle processor that s just executing instructions and as memories are also part of core so even data is also not an output I m working on implementation of some peripherals like UART SPI RAM etc I just try this design to understand the flow of Openlane so if I just add a dummy output variable will my design be able to complete the openlane flow

donn · Answer

yes

donn · Answer

To be precise the output variable needs to actually amtter

donn · Answer

If it s an empty wire it ll still be optimized out

Junaid amjad · Answer

like an empty wire will work or not

donn · Answer

It will not work

Junaid amjad · Answer

So I have to assign that output something that always going to get some value

donn · Answer

you have to assign it to something in your circuit like the read data from memory

Junaid amjad · Answer

Got you

Junaid amjad · Answer

thanks < donn>