All previous steps are completed successfully but I m gettin open-source-silicon.dev #sky130

All previous steps are completed successfully but ...

Junaid amjad

12/30/2021, 7:41 AM

All previous steps are completed successfully but I'm getting error at routing, can anyone please guide me about this? Attached are the error and config.tcl screenshots

Hadir Khan

12/30/2021, 7:49 AM

What is your caravel-lite commit?

Vijayan Krishnan

12/30/2021, 8:01 AM

share runs/run1/openroad_issue_reproducible tar file

Vijayan Krishnan

12/30/2021, 8:02 AM

seems you're running estimate_parasitics -global_routing without running global_route

Junaid amjad

12/30/2021, 9:25 AM

@Vijayan Krishnan Sir kindly check it

file.

Vijayan Krishnan

12/30/2021, 9:51 AM

file format not support what you shared. share as zip or tar file

Junaid amjad

12/30/2021, 9:53 AM

@Vijayan Krishnan Sorry for inconvenience

file.tar.gz

Junaid amjad

12/30/2021, 9:56 AM

This file is fine or not? @Vijayan Krishnan

Vijayan Krishnan

12/30/2021, 10:07 AM

able to get same issue

Junaid amjad

12/30/2021, 10:09 AM

@Vijayan Krishnan Check now

openroad_issue_reproducible.zip

Junaid amjad

12/30/2021, 10:12 AM

@Hadir Khan right now I'm just running the openlane flow (not caravel flow)

✅ 1

Vijayan Krishnan

12/30/2021, 10:12 AM

am able to reproduce your issue at my end

Vijayan Krishnan

12/30/2021, 10:12 AM

working on that.

Vijayan Krishnan

12/30/2021, 10:21 AM

can you share your config.tcl, so it will be easy to find what are additional settings you added

Junaid amjad

12/30/2021, 11:53 AM

BTW I have attached a screenshot of config.tcl @Vijayan Krishnan But let me send you the complete file as well

Junaid amjad

12/30/2021, 11:54 AM

I really appreciate your time @Vijayan Krishnan

Junaid amjad

12/30/2021, 11:54 AM

I'm stuck at routing for like now two days

Junaid amjad

12/30/2021, 11:55 AM

I'm trying different variables at different steps but it's not working

Junaid amjad

12/30/2021, 11:58 AM

@Vijayan Krishnan

config.tcl

Vijayan Krishnan

12/30/2021, 12:01 PM

set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0 add this in config.tcl and try once

Junaid amjad

12/30/2021, 12:29 PM

Now getting this error at routing @Vijayan Krishnan

Junaid amjad

12/30/2021, 12:39 PM

https://github.com/EmJunaid/Risc-V-32I-Single-Cycle-Processor.git

Vijayan Krishnan

12/30/2021, 12:40 PM

Copy code

# User config
set ::env(DESIGN_NAME) main

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# Fill this
set ::env(CLOCK_PERIOD) "100"
set ::env(CLOCK_PORT) "clk"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2920 3520"
set ::env(RUN_CVC) 0

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}

Junaid amjad

12/30/2021, 12:40 PM

@Vijayan Krishnan If you have time can you take a look at above my repo and guide me about it like which variables should I use to run the flow

Vijayan Krishnan

12/30/2021, 12:41 PM

try this config.tcl once and let me know

Vijayan Krishnan

12/30/2021, 12:42 PM

which openlane version are you using?

Junaid amjad

12/30/2021, 12:44 PM

I just installed it a week ago tbh I don't know which version is this

Junaid amjad

12/30/2021, 12:44 PM

but I think this must be the latest bcz I installed just a week ago

Vijayan Krishnan

12/30/2021, 12:45 PM

in the repo link which is your top design

Junaid amjad

12/30/2021, 12:46 PM

top_level.v

Vijayan Krishnan

12/30/2021, 12:46 PM

i'm updating my openlane repo now. Update you once i check it

Junaid amjad

12/30/2021, 12:47 PM

In instruction_memory.v I read machine code from .mem file so if you will not add that file it will give error

Junaid amjad

12/30/2021, 12:48 PM

let me send you instruction_memory.v file with some hard code machine codes

Junaid amjad

12/30/2021, 12:49 PM

@Vijayan Krishnan you can use this

Instruction_Memory.v

Vijayan Krishnan

12/30/2021, 12:51 PM

👍

Junaid amjad

12/30/2021, 12:57 PM

getting same estimating parasitic error with your config.tcl as well

Vijayan Krishnan

12/30/2021, 1:23 PM

11. Executing Verilog-2005 frontend: /openlane/designs/risc32_scp/src/Controller.v /openlane/designs/risc32_scp/src/Controller.sv2v.v12 ERROR: syntax error, unexpected TOK_CHECKER, expecting TOK_ID or '#' [ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /openlane/designs/risc32_scp/runs/1strun/logs/synthesis/1-synthesis.log |& tee >&@stdout"

Vijayan Krishnan

12/30/2021, 1:23 PM

facing issue at synthesis itself

Junaid amjad

12/30/2021, 1:24 PM

let me send you updated file

Junaid amjad

12/30/2021, 1:26 PM

use this file, although it does not have any syntax error earlier as well but I don't know why it gave this syntax error

Controller.v

Junaid amjad

12/30/2021, 1:26 PM

but with this file you will not get this syntax error @Vijayan Krishnan

Vijayan Krishnan

12/30/2021, 1:54 PM

I'm not able to get same error with the repo.

Copy code

config: /openlane/scripts/openroad/pdn_cfg.tcl
[ERROR PDN-0085] Pitch 3.6799999999999997 specified for layer met4 is less than 2 x (width + spacing) (width=3.0, spacing=1.84).
Error: pdn_cfg.tcl, 39 PDN-0085

Junaid amjad

12/30/2021, 2:03 PM

so noe what is this error?

Junaid amjad

12/30/2021, 2:03 PM

and can you share your config.tcl

Vijayan Krishnan

12/30/2021, 2:11 PM

# Change if needed set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v] # Fill this set ::env(CLOCK_PERIOD) "10.0" set ::env(CLOCK_PORT) "clk" set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl if { [file exists $filename] == 1} { source $filename } set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" #set ::env(FP_SIZING) absolute #set ::env(DIE_AREA) "0 0 2920 3520" set ::env(RUN_CVC) 0 set ::env(FP_PDN_CORE_RING) 1 set ::env(FP_PDN_CORE_RING_VWIDTH) 3 set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH) set ::env(FP_PDN_CORE_RING_VOFFSET) 14 set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET) set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING) set ::env(FP_PDN_VWIDTH) 3 set ::env(FP_PDN_HWIDTH) 3 set ::env(FP_PDN_VOFFSET) 5 set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET) set ::env(FP_PDN_VPITCH) 180 set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH) set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)] set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)] set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}] set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}] set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" set ::env(FP_PDN_CHECK_NODES) 0

Vijayan Krishnan

12/30/2021, 2:30 PM

seems i'm running wrong repo of verilog source code. zero instance found from the top file you gave. Please provide right src zip file

Junaid amjad

12/30/2021, 2:38 PM

source repo is upto date

Junaid amjad

12/30/2021, 2:38 PM

there might be some other issues

Vijayan Krishnan

12/30/2021, 2:42 PM

Copy code

30. Printing statistics.

=== risc32_scp ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

Vijayan Krishnan

12/30/2021, 2:42 PM

no cells found from your verilog code. I just changed top module name main to risc32_scp

Junaid amjad

12/30/2021, 2:45 PM

so what does this mean?

Junaid amjad

12/30/2021, 2:46 PM

like my verilog files are wrong?

Vijayan Krishnan

12/30/2021, 2:48 PM

can you share your runs/logs/synthesis/1_synthesis.log

Junaid amjad

12/30/2021, 2:50 PM

1-synthesis.log

Vijayan Krishnan

12/30/2021, 2:51 PM

same in your end aslo

Copy code

Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

Junaid amjad

12/30/2021, 2:53 PM

it is tested design through vivado

Junaid amjad

12/30/2021, 2:54 PM

i have syhthesised it using vivado and it's fine

Junaid amjad

12/30/2021, 2:55 PM

what do you think issue might be?

Junaid amjad

12/30/2021, 2:55 PM

bcz it's a tested design

Junaid amjad

12/30/2021, 2:56 PM

ok so what can you infer through errors which you are getting during flow?

Junaid amjad

12/30/2021, 2:57 PM

all files are completely in verilog

Vijayan Krishnan

12/30/2021, 2:58 PM

using the repo source file, zero instance used, so tool not doing any placement

Vijayan Krishnan

12/30/2021, 2:58 PM

first time am seeing this error. Raise github issue, some one will guide you

Junaid amjad

12/30/2021, 3:00 PM

BTW you are purely backend engineer?

Vijayan Krishnan

12/30/2021, 3:00 PM

yes

Junaid amjad

12/30/2021, 3:01 PM

you have also happened to work on cadence tools?

Junaid amjad

12/30/2021, 3:02 PM

can you give me your email id bcz I have couple of other desighns as well like 5 stage pipeline and I'm also implementing some peripherals as well so will you be willing to help me with them if I need any?

Vijayan Krishnan

12/30/2021, 3:05 PM

you can DM here itself or raise github, other experts will help you

Junaid amjad

12/30/2021, 3:14 PM

ok can you share some backend resources for beginners

Junaid amjad

12/30/2021, 3:15 PM

like there is almost nothing available when it comes to backend

Vijayan Krishnan

12/30/2021, 3:17 PM

https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src refer each tool READEME.md here

Vijayan Krishnan

12/30/2021, 3:17 PM

https://openroad.readthedocs.io/en/latest/main/README.html

Junaid amjad

12/30/2021, 3:20 PM

ok I really appreciate your time,

Junaid amjad

12/30/2021, 3:20 PM

thank you so much

Junaid amjad

12/30/2021, 3:21 PM

I try to find out like what is the issue in verilog files

Vijayan Krishnan

12/31/2021, 10:40 AM

@Junaid amjad I checked with Frontend team. The verilog looks ok. But during yosys synthesis top level unconnected signals removed by OPT_CLEAN.

Copy code

15.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
Removed 1010 unused cells and 1736 unused wires.
<suppressed ~1104 debug messages>

Need to find option to skip this

Junaid amjad

01/03/2022, 6:02 AM

@Vijayan Krishnan So what do I need to do now?

Junaid amjad

01/03/2022, 6:03 AM

like you are saying that my top level connections are wrong or what?

Vijayan Krishnan

01/03/2022, 6:34 AM

https://github.com/The-OpenROAD-Project/OpenLane/issues/834 tag yourself here and follow-up

Vijayan Krishnan

01/03/2022, 10:50 AM

@Junaid amjad can you tag yourself in the above github issue. Answer the experts question, so it will be resolved else it will be closed

donn

01/03/2022, 11:30 AM

@Junaid amjad

Junaid amjad

01/03/2022, 12:42 PM

@donn yes you are right, design does not has any output because it's very basic level single cycle processor that's just executing instructions and as memories are also part of core so even data is also not an output. I'm working on implementation of some peripherals like, UART, SPI, RAM etc. I just try this design to understand the flow of Openlane. so if I just add a dummy output variable, will my design be able to complete the openlane flow?

donn

01/03/2022, 12:42 PM

yes.

donn

01/03/2022, 12:42 PM

To be precise, the output variable needs to actually amtter

donn

01/03/2022, 12:42 PM

If it's an empty wire, it'll still be optimized out

Junaid amjad

01/03/2022, 12:44 PM

like an empty wire will work or not?

donn

01/03/2022, 12:44 PM

It will not work.

Junaid amjad

01/03/2022, 12:45 PM

So I have to assign that output something that always going to get some value

donn

01/03/2022, 12:46 PM

you have to assign it to something in your circuit. like the read data from memory

Junaid amjad

01/03/2022, 12:51 PM

Got you

Junaid amjad

01/03/2022, 12:51 PM

thanks @donn

Open in Slack

Previous Next