In a 3-well process (nwell, pwell, deep nwell) the...
# sky130
In a 3-well process (nwell, pwell, deep nwell) there are 5 types of diodes. pdiff - nwell, pwell - ndiff, psub - nwell, pwell - deep nwell, psub - deep nwell (if psub is not virtually split, psub - nwell and psub - deep nwell are electrically equivalent). From what I can see, the magic extraction rules only handle pdiff - nwell and pwell - ndiff. @User Is this correct?
Yes. This is based on what SkyWater considers a "device" vs. a "parasitic". There are a few situations for which there is a diode device ID layer that can be used to specify that a certain P-N junction is to be extracted as a device. Otherwise, it gets into the general problem of having to determine when a P-N junction is part of a device model and when it isn't. For all of the transistors, the source and drain diffusion diodes to well or substrate should be in the model, meaning that mostly only well to substrate diodes are not being either extracted or modeled. Unless you're specifically simulating latch-up, or have wells not connected to a rail voltage, then representing the diodes as parasitic devices in the netlist isn't going to make a lot of difference to a simulation.
Unless you're specifically simulating latch-up, or have wells not connected to a rail voltage,
Or have the wells connected to the wrong voltage (which CVC checks if the diodes are in the netlist). Related to the question in the other thread about INTERACT, in the past, I've extracted diodes by using layers calculations like
ndiode = (ndiff NOT INTERACT poly) and pwell
without the need for a recognition layer. Is there some way in magic to select the
that is not part of transistors? I feel that using a recognition layer for diodes may be dangerous because there may be diodes in the layout that aren't extracted. Using a recognition layer for bipolar devices (to distinguish from plain diodes) may be necessary, though. I've gotten the
pads in caravel's
to pass LVS, but the
pad diodes are not extracting as expected. The nwell taps surrounded by
appear to be extracted as
and I can't figure out why (the presence of NWEL should prevent this).
@User I think I found the (a) problem. The
cell is completely surrounded by the
recognition layer. In magic, this appears to treat all the diffusion as diodes (including the nwell taps!). As such, after reading the gds into magic, you can see
generated under the
, (possibly because it sees the
as an
) when I think they're supposed to be mutually exclusive. Here's a screen shot of the magic view. The gds only has
. I'm going to try to cut the recognition layer so that it only covers the actual diodes.
@User: Use a rule like
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templayer fet_diff
bloat-all allfets alldiff
Then for diodes, do an AND-NOT with
to exclude all diffusion belonging to FET devices. I'm not sure how that works in practice. Technically, I would say that dropping the
ID layer on top of transistors is just an error.
Ok, by modifying the diode recognition layer to cover only the actual diodes in
(and not the nwell tap), the layout extracted as expected. However, it did not pass LVS. The
file has
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* sky130_ef_io__vssd_lvc_clamped_pad
* sky130_ef_io__vssd_lvc_pad with LV clamp connections to VCCD and VSSD,
* and back-to-back diodes connecting VSSD to VSSIO
but it appears that the back-to-back pd-nwell diodes are
. The surrounding psubstrate is
, however. Checking the other
power pads now.
is missing the
subckt definition, so I added it. It contains the back-to-back pd-nwell diodes.