In a 3-well process (nwell, pwell, deep nwell) there are 5 types of diodes. pdiff - nwell, pwell - ndiff, psub - nwell, pwell - deep nwell, psub - deep nwell (if psub is not virtually split, psub - nwell and psub - deep nwell are electrically equivalent). From what I can see, the magic extraction rules only handle pdiff - nwell and pwell - ndiff. @User Is this correct?

Yes. This is based on what SkyWater considers a "device" vs. a "parasitic". There are a few situations for which there is a diode device ID layer that can be used to specify that a certain P-N junction is to be extracted as a device. Otherwise, it gets into the general problem of having to determine when a P-N junction is part of a device model and when it isn't. For all of the transistors, the source and drain diffusion diodes to well or substrate should be in the model, meaning that mostly only well to substrate diodes are not being either extracted or modeled. Unless you're specifically simulating latch-up, or have wells not connected to a rail voltage, then representing the diodes as parasitic devices in the netlist isn't going to make a lot of difference to a simulation.

Unless you're specifically simulating latch-up, or have wells not connected to a rail voltage,

Or have the wells connected to the wrong voltage (which CVC checks if the diodes are in the netlist). Related to the question in the other thread about INTERACT, in the past, I've extracted diodes by using layers calculations like

ndiode = (ndiff NOT INTERACT poly) and pwell

without the need for a recognition layer. Is there some way in magic to select the

ndiff

that is not part of transistors? I feel that using a recognition layer for diodes may be dangerous because there may be diodes in the layout that aren't extracted. Using a recognition layer for bipolar devices (to distinguish from plain diodes) may be necessary, though. I've gotten the

hvc

pads in caravel's

chip_io

to pass LVS, but the

lvc

pad diodes are not extracting as expected. The nwell taps surrounded by

DIODE

appear to be extracted as

sky130_fd_pr__diode_pw2nd_05v5

and I can't figure out why (the presence of NWEL should prevent this).

@User: Use a rule like

templayer fet_diff
bloat-all allfets alldiff

Then for diodes, do an AND-NOT with

fet_diff

to exclude all diffusion belonging to FET devices. I'm not sure how that works in practice. Technically, I would say that dropping the

DIODE

ID layer on top of transistors is just an error.

Ok, by modifying the diode recognition layer to cover only the actual diodes in

sky130_fd_io__gnd2gnd_120x2_lv_isosub

(and not the nwell tap), the layout extracted as expected. However, it did not pass LVS. The

sky130_ef_io.spice

file has

*-------------------------------------------------------------------------- 
* sky130_ef_io__vssd_lvc_clamped_pad
* sky130_ef_io__vssd_lvc_pad with LV clamp connections to VCCD and VSSD,
* and back-to-back diodes connecting VSSD to VSSIO
*--------------------------------------------------------------------------

but it appears that the back-to-back pd-nwell diodes are

VSSA

to

VSSIO

. The surrounding psubstrate is

VSSD

, however. Checking the other

lvc

power pads now.