Hi everyone! My question has to do with the range of parasitic capacitances on the FETs compared to the smallest values of mimcaps. For example, my design requires a capacitances of ~3fF and I was wondering if this is too small to get affected by the parasitics on FETs. I tried to do the layout and extract the values of capacitances. In the ext file, I see these lines: cap "a_560_0#" "a_560_200#" 10.7812 cap "a_0_0#" "a_n400_0#" 3.23243 cap "a_0_0#" "a_0_200#" 10.7812 Do these values in any way reflect the parasitic capacitance values? If so, what are the units? My second question is: What is the largest recommended value of capacitance on the mimcap? Can we go to tens of picofarads? Or are there some practical considerations to be mindful of. Thank you!

Wire parasitic capacitances will be larger than 3 fF.

@User: If the 2nd number in the "scale" line at the top of the .ext file is 1 (which it should be for sky130), then the value used in a "cap" line is in attoFarads.

"scale 1000 1 500000" I see that it is the above line. So I guess the value is in atto farads. Right? @User can you please also clarify on the largest size of caps that are advisable to use?

@User: There is a practical limit enforced by the metal density rules for the MiM cap top or bottom plate (whichever one hits the limit first). Given a large area of caps, the largest value of the bottom plate with minimum spacing in between of 1.2um that yields just less than 60% density is 5.32um x 5.32um, so that's what I would suggest as an upper limit if you don't want to run afoul of density rules. There are also delamination risks, although there is no mention of that in the SkyWater rules, maybe because the metal density rules prohibit the generation of any cap that would have delamination issues. Based on other similar foundry processes and rules, though, I would suggest a strict upper limit of 30um x 30um for a single MiM capacitor. Of course, you can double the amount of capacitance by using both of the stacked MiM caps, and if you're keeping below the metal density threshold, then you can array them over as large an area as you want.

Does the DRC in magic enforce the density rules? It seems to me I can create metal plates larger than 30x30um². How to check if I'm violating the density rules?

@User: Magic does not check density rules by the standard DRC engine. For density rule checks, use the script in open_pdks:

${PDK_PATH}/libs.tech/magic/check_density.py

. This should be run on a GDS file after running fill pattern generation. Preferably the file should represent the full chip, or results are not necessarily accurate. If you don't run fill pattern generation first, then you should still be able to check the result of the script for over-density errors.