Hi everyone, when i do in Magic: extract do local extract all ext2spice lvs ext2spice The inductor from ASITIC isn's recognized as a subcircuit. Could someone help me?

Are there power switches in the sky130 library?

Hey I'm facing some problem in the execution of a simple mux design in openplane.

Core area width: 11.04 [INFO]: Core area height: 10.88 [WARNING]: Current core area is too small for a power grid [WARNING]: !!! THE POWER GRID WILL BE MINIMIZED. !!! [INFO]: Final Vertical PDN Offset: 1.8399999999999999 [INFO]: Final Horizontal PDN Offset: 1.8133333333333335 [INFO]: Final Vertical PDN Pitch: 3.6799999999999997 [INFO]: Final Horizontal PDN Pitch: 3.626666666666667

i'm getting this info regarding the pdn of my design but while generating the pdn it gives the fiollowing error: Power Delivery Network Generator: Generating PDN config: /openlane/scripts/openroad/pdn_cfg.tcl [ERROR PDN-0085] Pitch 3.6799999999999997 specified for layer met4 is less than 2 x (width + spacing) (width=1.6, spacing=1.84). Error: pdn_cfg.tcl, 40 PDN-0085 [ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child process exited abnormally, how can i resolve this issue?

First fully-testable user project, from ChipIgnite 1! Congratulations to @User!

Hi, I got this error "Can't open ABC output file" when running "abc -liberty cells.lib" on Yosys. Is it because of using "cells.lib"? How to fix it? When I run it directly after "read_verilog" before "synth -top" I got "skipping model as it contains processes" I can't understand it, any explanation, please? What is the command to download libs (sk130) I only have "cells.lib", please?

Hi, How does the sizing work for NMOS and PMOS devices? I originally thought the sky130 meant the smallest channel length would be 130nm, but it seems that devices like nfet_01v8 have a default L of 0.15 in xschem. Is that shortest length, or is it okay to change it to 130nm?

Hello, what are the standard values for Kn' for NMOS and Kp' for PMOS for 130nm PDK. These values should be constant for PDK am I right? @User

Sort of a general question/warning. On the caravel/caravan framework, there are two 3.3V sources, vdda1 and vdda2. Circuits using these voltages should be using

sky130_fd_sc_hvl

, correct? All the other standard cell libraries only have 1.8v rated mosfets.

How to start klayout tool in OpenLane?

Somebody knows if exists a video/doc which shows the step-by-step (in pratice) how to connect our project on efabless chip and run the other necessary steps to complete the tapeout?

Is it possible to speed up analog sims in ngspice? I mean, in particular, I believe the first part takes quite long because it fetches the

.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt

However in my case I have a relatively small circuit which only uses two types of devices, sky130_fd_pr__nfet_01v8 and sky130_fd_pr__pfet_01v8, so I wonder is it possible to get it to fetch only those devices used in the circuit? Even telling it somehow. That would speed things up a lot, in particular for quick iteration (optimization) over a circuit. Otherwise every time I make a small change on the circuit the sim takes a few minutes to run, which is quite impractical. I'm pretty sure somebody has encountered this issue before. Is there a way to do this, to speed up the simulation cycle speed? Thanks

Hi everyone, anyone has details on how I can sign the NDA to get access to the sky130 tech with commercial tools? (Through university)

does the SKY130 process support depletion-mode fet?

(trying to reproduce the circuit from the first chapter of the "Introduction to VLSI systems" book)

Hi, I tried to run a post-layout (with RC extraction) simulation but I got an error due to mosfets that has w = 0 l = 0 in the netlist. How can I resolve this problem?

In the .pm3.spice files, there are the threshold voltage values but defined with another variable (such as "sky130_fd_pr__ nfet_ 01v8__ vth0_diff_1) that doesn't seem to be defined in the file. Is there a way to find that value? Or is there a document with some of the general transistor parameters (threshold voltage, mobility..)?

Hi guys, the mosfet is a simmeteycal device(Drain and Source can be exchanged on layout) , right? But when i do LVS in netgen, i need to Flip some mosfets around their gates to fix match problems even if the LVS has the same nets and devices. Could i consider the mosfet as simmetrycal in LVS?

Hi, is it possible to have an nmos (nfet_01v8) with 0.36um width & 0.15um length? When I was designing and simulating my schematic, I looked up the minimum width & length from the models (looked at the model bins in

/usr/local/share/pdk/sky130A/libs.ref/sky130_fd_pr/spice/sky130_fd_pr__nfet_01v8.pm3.spice

), and from there I gathered minimum width & length for the nfet_01v8 were 0.36um/0.15um. My circuit needs small devices to minimize capacitance on certain nodes for high speed, so I set some devices in my schematic to that size, and it simulated without issues. I designed & verified (pre-layout) my circuit with those dimensions, but then when I get to the layout stage, Magic says that "Mos width must be >= 0.42 um" for that device... And it won't let me draw a 0.36um wide device. Why is there this inconsistency between Magic and the Sky130 model files? Which one is correct/to be trusted? Thanks

Hi, when i try to extresist, i get this issues and no resistance are extracted in .spice, any idea?

Hi everyone, I have seen some SRAM macros in Open MPW 5 projects, such as riscduino, but I could not see any SRAM primitive in Skywater PDK files. Is there any primitive for SRAM in Skywater PDK? If yes, how can I use them?

@User,a 'software' question. Since linux is slowly switching from Xlib to Wayland do you have a roadmap for that? For Xschem: it draws directly using Xlib calls, and uses Tck-Tk for UI interface (menu, dialogs etc) For the Xlib phase out the easy path for xschem drawing is to switch to Cairo graphics, this is already done in xschem to draw text and images, so swicthing the remaining primitives (lines, polygons, etc) to cairo is easy (i expect a performance degradation however). For the Tcl-Tk UI i don't know, as i don't see any plan for migrating to Wayland. This is sad since in 20 years the Tcl API has been really stable and today xschem compiles and runs fine with all tcl-tk versions from 8.6+ back to 8.4 which was used ~20 years ago. See any gtk project and how much work has to be done any time a gnome/gtk dev wakes up in the morning and changes/deprecates random parts of the core C API. I believe Magic also uses tcl for many UI parts so just curious what are your thoughts.

When i run make run-precheck from https://github.com/efabless/caravel_user_project_analog/blob/main/docs/source/index.rst i get this Erro 2

Hi everyone! My question has to do with the range of parasitic capacitances on the FETs compared to the smallest values of mimcaps. For example, my design requires a capacitances of ~3fF and I was wondering if this is too small to get affected by the parasitics on FETs. I tried to do the layout and extract the values of capacitances. In the ext file, I see these lines: cap "a_560_0#" "a_560_200#" 10.7812 cap "a_0_0#" "a_n400_0#" 3.23243 cap "a_0_0#" "a_0_200#" 10.7812 Do these values in any way reflect the parasitic capacitance values? If so, what are the units? My second question is: What is the largest recommended value of capacitance on the mimcap? Can we go to tens of picofarads? Or are there some practical considerations to be mindful of. Thank you!

After do make run-precheck in caravel analog, should i run make xor-analog-wrapper too? My project is 100% analog.

Hi everyone! While running make pdk the script gets stuck trying to load some magic-related file. Has anyone faced this before and knows the fix for this?

Hi all! Does anyone know what is the value I should set to the GOLDEN_CARAVEL variable during make run-precheck? The make command fails for me without showing any specific error, so I believe it is related to not setting that environment variable as the messages show.

I'm running into a DRC violation when creating varactors with magic: N-well overalp of varactor poly <0.15um. I'm not sure what to do. It seems to me the generated varactor is faulty.

Are the 1.8V PFET/NFET bins listed somewhere convenient on the web? (I notice that the PFET spice file doesn't have them in comments to easily grep...)