Hi, I am trying to compile a dual-port SRAM with one read/write and one read port targeting the Skywater 130nm technology. I have the following questions. 1. Is there a limit to the SRAM size, in terms of the number of bits? 2. I did not find the complete library for Sky130 in the github clone of OpenRAM: https://github.com/VLSIDA/OpenRAM Is it available somewhere, or is there a way to build/generate the missing library cell folders like gds_lib, sp_lib, tf, etc., in the technology/sky130 folder? I did find a repo where this is probably done but I am not sure if it has the most updated libraries: https://github.com/vsdip/vsdsram_sky130/tree/main/OpenRAM/sky130A I succeeded in building a single ported (1 RW) SRAM with32768 bits (32x1024) using the files from the above mentioned repo. Next I modified the config file fields accordingly to compile a dual-ported SRAM (RW=1, R=1) of size 32768 bits:

word_size=32
num_words=1024
num_rw_ports = 1
num_r_ports = 1
write_size = 4
tech_name="sky130A"
process_corners=["TT"]
supply_voltages=[1.8]
output_path="sky130_ram_32x1024_1rw_1r"
output_name="sram_{0}{1}{2}".format(word_size,num_words,tech_name)

But I get the following error:

** Start: 02/27/2022 21:18:17
Technology: sky130A
Total size: 32768 bits
Word size: 32
Words: 1024
Banks: 1
Write size: 4
RW ports: 1
R-only ports: 1
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
ERROR: file design.py: line 46: Custom cell pin names do not match spice file:
['bl0', 'br0', 'bl1', 'br1', 'wl0', 'wl1', 'vdd', 'gnd'] vs []
Traceback (most recent call last):
 File "/home/anuj/OpenRAM/compiler/openram.py", line 54, in <module>
  c = sram_config(word_size=OPTS.word_size,
 File "/home/anuj/OpenRAM/compiler/sram/sram_config.py", line 44, in _init_
  self.compute_sizes()
 File "/home/anuj/OpenRAM/compiler/sram/sram_config.py", line 73, in compute_sizes
  bitcell = factory.create(module_type=OPTS.bitcell)
 File "/home/anuj/OpenRAM/compiler/sram_factory.py", line 142, in create
  obj = mod(name=module_name, **kwargs)
 File "/home/anuj/OpenRAM/compiler/bitcells/bitcell_2port.py", line 22, in _init_
  super()._init_(name, prop=props.bitcell_2port)
 File "/home/anuj/OpenRAM/compiler/bitcells/bitcell_base.py", line 21, in _init_
  design.design._init_(self, name, cell_name, prop)
 File "/home/anuj/OpenRAM/compiler/base/design.py", line 46, in _init_
  debug.check(prop.port_names == self.pins,
 File "/home/anuj/OpenRAM/compiler/debug.py", line 33, in check
  assert 0
AssertionError

So I was wondering if someone could help me compile a dual-ported SRAM with the (preferably recent) Sky130 library cells. Thanks!

@User You might try asking on #openram. By the way, there are precompiled sram macros available for mpw-5.

sky130_sram_1kbyte_1rw1r_32x256_8.gds
sky130_sram_1kbyte_1rw1r_8x1024_8.gds
sky130_sram_2kbyte_1rw1r_32x512_8.gds

Clone the

caravel_user_project

repo. They should be in

$PDK_ROOT/sky130A/libs.ref/sky130_sram_macros

https://skywater-pdk.slack.com/archives/C0221Q4PYJ0/p1645902518520619

Thanks a lot @User for pointing me to the relevant channel and also to the precompiled macros. Since it only has precompiled macros of size 1kB, I'll most likely have to compile the rams of larger size myself.

There's a 2kB version too. You can download the gds to see the macro size.

Ahh yes! Thanks, Mitch! 🙂