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#sky130
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# sky130
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Redwan Islam

03/19/2022, 9:30 AM
Hi there!! also drawing attention @User Sir, I am a newbie in this group and better to say I'm new to IC design by open source tools. So recently I started to integrate Linux ubuntu on my VMware and then followed this tutorials https://www.udemy.com/course/vsd-a-complete-guide-to-install-open-source-eda-tools/ and successfully done everything but then followed https://www.udemy.com/course/vsd-a-complete-guide-to-install-openlane-and-sky130nm-pdk/ and i have done everything but in the last video I could not pull the docker as instructor also could not at first couple of attempt but then he did restart the system and said it worked this time which I did but for me did not work. Here I am attaching the screen shot of my terminal Apart from this, I would like to get help on how to start designing IC by all these open source tools? Some links or suggestions carrying complete guideline On IC design flow is what I needed. T.I.A.
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Arman Avetisyan

03/19/2022, 10:59 AM
The command you used contains an error: 1. You didn't pull the openlane:current. OR 2. Most likely you want to use efabless/openlane:current instead as it will pull the docker automaticcly
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Redwan Islam

03/19/2022, 11:12 AM
Can u tell me what is the right command plz?
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Arman Avetisyan

03/19/2022, 11:21 AM
replace openlane:current with efabless/openlane:current
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Redwan Islam

03/19/2022, 11:37 AM
Still same
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Arman Avetisyan

03/19/2022, 11:46 AM
try running docker pull efabless/openlane:current
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Redwan Islam

03/20/2022, 8:21 AM
Thank u, I think it worked.. Would u plz help me on how to start designing( i don't know anything about designing using open source tools) ICs using open source tools..plz..Need a complete guideline as a beginner(0 knowledge)
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Arman Avetisyan

03/20/2022, 8:40 AM
1. Decide what you want to do 2. If it's digital design go with digital design flow 3. If it's analog go with analog design flow Digital design flow: Use Iverilog to simulate your designs. Write verilog and verilog testbench. Preiodiclly synthesize the verilog to see how fast it is clock wise + how much area it takes. This can be done with OpenLane Analog design flow: Use xschem/ngspice to design schematic. Use NGSPICE to simulate your circuit with sky130 pdk installed + included. Make sure it works as you want it to. Then use KLayout to make a layout, use skywater's tech docs + Magic VLSI primitive generator. After the layout is done, complete DRC/LVS checks using Magic VLSI to DRC. Magic VLSI to extract the cirrcuit out of layout. Netgen to compare the circuits (netlists). There is plenty of tutorials for sky130 on all of this
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Kunal

03/20/2022, 11:06 AM
@User - can you please share your VSD workshop gitlab repo?
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Glenn Frey Olamit

03/20/2022, 11:07 AM
Hi @User as @User stated you can design analog and digital IC using those tools he mentioned but if you are designing a mixed IC I suggest you install eSim. ESim is integrated with kicad, and ngspice which is used in analog design and makerchip for digital design. You may want to check on my github repo named FSM in ASIC with RF transmitter to get a glimpse of eSim. If you are working on purely analog I suggest you look at BGR and PLL vsdiat workshop on my repo. That will walk you through the entirety of analog design from specification to layout. After that you are ready for Physical Design stage, https://github.com/glennfrey/Advanced-Physical-Design-Using-Openlane-Sky130 and then the Physical Verification stage https://github.com/glennfrey/Physical_Verification_using_Sky130.
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Kunal

03/20/2022, 2:08 PM
Correcting the Physical Verification workshop link - https://github.com/glennfrey/Physical_Verification_using_Sky130
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Redwan Islam

03/20/2022, 2:49 PM
Thanks a lot @User and @User for the guideline. I'll be in touch and will knock if I face any problem.
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Glenn Frey Olamit

03/21/2022, 5:06 AM
You’re welcome.