Will we be able get standard cell verilog model to include d open-source-silicon #sky130

Channels

caravel-documentation

mpw-6plus-silicon

pd-openlane-and-sky130

chipignite2206q_stanford_bringup

cadence-virtuoso

fossee-iitb-esim

dynamic-power-estimation

ieee-sscs-dc-23

gfmpw-0-silicon

silicon-validation

fossee-iitb-google-sky130

ieee-sscs-dc-22

mpw-one-silicon

cadence-innovus

verification-fe

foss-asic-tools

openpositarithmetic

openadiabaticlogic

hardware-beginners

design-services

private-shuttle

tapeout-pakistan

rad-lab-silicon

cadence-spectre

mpw-one-clean-short

coalition-for-digital-environmental-sustainability

vlsi_verilog_using_opensource_eda

vlsi_verilog_using_opensoure_eda

openlane_cloudrunner

digital-electronics-learners

verilog-learners

open-microelectronics-textbook

mwcas-2023-rtl2silicon

system-verilog-learners

vlsi-learners-group

chilechipmakers

silicon-validation-private

openhighqualityresonators

waveform-viewers

vendor-synopsys

silicon-photonics

opendataset-circuitnet-for-ml-tasks-in-vlsi-cad

community_denmark_dtu

shuttle-precheck

openlane-development

ieee-sscs-dc-21q3

sky130-pv-workshop

verification-be

Title

# sky130

c

Can Wang

04/12/2022, 7:35 PM

Will we be able get standard cell verilog model to include delay information so that we can run .SDF back-annotated gate-level simulation?

@User In case Tim are flooded by messages.😃

t

Tim Edwards

04/13/2022, 10:07 PM

Ask Mohamed Shalan. He has done full SDF back-annotated simulation (with "cvc" from Tachyon Design Automation).

✅ 1