Will we be able get standard cell verilog model to...
# sky130
c
Will we be able get standard cell verilog model to include delay information so that we can run .SDF back-annotated gate-level simulation?
@User In case Tim are flooded by messages.😃
t
Ask Mohamed Shalan. He has done full SDF back-annotated simulation (with "cvc" from Tachyon Design Automation).
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