Will we be able get standard cell verilog model to include d open-source-silicon.dev #sky130

Will we be able get standard cell verilog model to...

Can Wang

04/12/2022, 7:35 PM

Will we be able get standard cell verilog model to include delay information so that we can run .SDF back-annotated gate-level simulation?

Can Wang

04/13/2022, 7:15 PM

@User In case Tim are flooded by messages.😃

Tim Edwards

04/13/2022, 10:07 PM

Ask Mohamed Shalan. He has done full SDF back-annotated simulation (with "cvc" from Tachyon Design Automation).

✅ 1