<@U016B4S5Z9U> Thank you for your presentation on ...
# sky130
@User Thank you for your presentation on adders. Regarding your slides, the timings (worst path delay) given on slides 12 and 13: what is the PVT corner considered? (Process corner - Voltage - Temperature)? Are layout parasitics included ? are these results of spice transistor level simulations or Verilog (or STA) simulations, including SDF annotation? Thank you so much for sharing your great work.
Hi Stefan! Thank you for xschem! The result were generated using the flow in this repo: https://github.com/tdene/adder_networks That is to say, they are OpenLane place-and-route results in the "typical" corner of TT, 25C, 1.8V. Layout parasitics are included, evaluated using OpenROAD, thus OpenRCX (last I checked this may differ from proprietary tools' RCX a little, but not by much). So SPEF-annotated STA.
Now, there's several things to say about that. First off, the driving load on the input pins and driven load on the output pins are taken as the defaults in this OpenLane flow. In turn, so are several other important flow parameters. These all have a large effect on the results. Second off, the adders are implemented as PnR'd hard macros. The pins are assumed to sit on certain layers, the routing tool has to route module inputs/outputs to the floorplan perimeter, etcetera. All this makes the numbers somewhat subjective, as all layout numbers are. Doing a straight spice simulation would indeed give more implementation-agnostic numbers. But the goal here was to provide practical numbers that show a comparison that would be relevant to users of an open-source synth + PnR flow, rather than the more scientific numbers of "how do these circuits behave in an objective vacuum".
I'm not at all saying that raw spice numbers aren't useful; quite the opposite. That just wasn't the primary audience.
As for the single result I show from the proprietary tools. That was obtained by synthesizing
on the same cell library and technology via proprietary synthesis tool, and taking that synthesized netlist through OpenLane's PnR steps. Meant to emulate as closely as possible the process used to generate the other results.
Looks like that result is on slide 11; the star on that graph.
@User Very clear! Thank you!