Iain Craig
08/14/2020, 9:41 AMmodule dual_port_ram(clock, read_addr, read_data, write_addr, write_data, write_enable);
parameter MEM_SIZE = 65535;
parameter WORD_SIZE = 8;
input clock, write_enable;
input [WORD_SIZE-1:0] read_addr, write_addr, write_data;
output reg [WORD_SIZE-1:0] read_data;
reg [WORD_SIZE-1:0] ram [0:MEM_SIZE];
always @(posedge clock) begin
if (write_enable) begin
ram[write_addr] <= write_data;
end
end
always @(posedge clock) begin
read_data <= ram[read_addr];
end
endmodule
Trevor Clarke
08/14/2020, 1:24 PMIain Craig
08/14/2020, 1:30 PM