oops....apparently autocomplete missed your name @User

this can also sometimes happen with positional ports...make sure hierarchy is executed in yosys after loading

Thanks for the hint @User, I'll check around that -- I thought I have them assigned to registers but must have missed something

I didn't get a chance to look over your code but those are common issues

one thing you can do to debug is execute "flatten" in yosys and look at the result (that flattens out the hierarchy and changes multi-wire assignments to a set of single assignments)

brilliant, thanks; I've just persuaded EDAPlayground's yosys to finally spit out a diagram of the logic, which is super helpful

I'll figure out how to do the same with OpenLANE's version -- EDAPlaygrounds' doesn't complain about undriven wires

to interactive mode I go

Hello everyone. Is there any resource from where I can learn hands on about all the processess from synthesis to checkout in ASIC design. I have a litte bit experience in verilog and am looking to expand my practical knowledge in digital design

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I know there are license considerations, but will and which versions of PCI Express plan to be supported?

Someone's got a 7Ghz clock modeled already

I’m new here and this is my intro. I just started learning about FPGAs and want to do small designs (up to 2,000 gates), some in Verilog and others in schematics. I’m currently researching the best tools, courses, and boards. All advice welcome! I’m currently watching a course .

This doesn’t seem to be the most popular channel for hardware beginners. Any other places people like?

The tutorial workshop sessions seem popular

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I have some questions about layouting best practices, not sure if here is the place for this, but: 1. Should vias be built as matrix of squares or shuld they fill all the available area? As an example, I am routing the drain of a FET out to a resistor going from metal1 to metal2 just over the transistor area, should I draw via1 as a big rectangle over the entire area or place multiple 0.26x0.26 squares inside a metal1/metal2 rectangle? 2. Should I avoid routing over the transitor active area, even on metal2? 3. Do metal/via overlap need to be only in one direction? DRC points its ok if I draw the metals extending only in one direction, should I always trust that if DRC is ok it will work? 4. Via/metal current limits per area, where to find them? Thanks in advance! Maybe I should post this on sky130? Don't know if these things are specific or just general IC layout practices.

ccDid everyone see @Matt Venn's TinyTapeout project? https://mailchi.mp/574276e3c9d7/tinytapeout?mc_cid=28ec6db3c0&mc_eid=d16f71268b

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