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#analog-design
Title
# analog-design
u

20Mhz

07/24/2020, 9:52 PM
@User, it seems VERILOG_INCLUDE_DIRS is not supported on this release of the scripts, I guess I can copy open road implementation to synth.tcl & synth_top.tcl
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set vIdirsArgs ""
if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
  foreach dir $::env(VERILOG_INCLUDE_DIRS) {
    lappend vIdirsArgs "-I$dir"
  }
  set vIdirsArgs [join $vIdirsArgs]
}


# read verilog files
foreach file $::env(VERILOG_FILES) {
  read_verilog -defer -sv {*}$vIdirsArgs $file
m

mkk

07/24/2020, 9:57 PM
That would make sense. I took a note. Feel free to put an issue even if it an enhancement
👍 1
u

20Mhz

07/24/2020, 10:16 PM
just realized I sent to the wrong channel, if this can be moved, great, otherwise, apologies for the spam.