has anyone been working on and opamp designs?

@Trevor Clarke I have been looking at Current Conveyer designs using the standard cells.

I'm only somewhat familiar with CCs...If I understand correctly, different configurations of external components and they behave as various sources and amps? Are they differential? I'm looking to create a voltage reference and the standard implementation usually requires an opamp as a differential amp

I'm not convinced you can get very far on the op-amp front without the spice models. Sure, you can draw up the schematics, maybe floorplan a layout but most of the design has to wait for the models

I agree you need to simulate, but starting with a design (including sizes) from another 130nm process is a reasonable starting point to get a bit further than just a floorplan

ignoring the differences between processes where would you get your hands on another 130 nm process?

there are papers available for 130nm opamp designs....my assumption was that any 130nm process is likely to result in the right order of magnitude for sizes such that leaving somewhat generous gaps between elements would allow tuning of the sizes for the specific process...is this an off-base assumption?

I guess it comes down to what performance you need/expect. Typically people would use the topology/design that's optimum for the task and that usually doesn't mean using "any old" design. But... having said all that, that's the "old" way of thinking which this community doesn't necessarily need to be limited to so maybe it's possible to get the performance required with a less rigorous approach. If it was me, I would leave a bit of time to come back and check all the biasing and stability at the very least once the models are available.

my understanding is that until somewhat recently lambda rules were often used to make designs somewhat process agnostic...they didn't make the most efficient designs so now it's more tailored to the process...since we don't have the characterizations yet I figured it might be reasonable to start with something more like that and get cells that do the job without meeting any particularly strict spec so there are some cells ready to test for november

I think that depend somewhat on your definition of how long ago 'recently' was... However, indeed I understand your approach. I've got a number of schematics setup just waiting for sizings (including an opamp). And working on layout setup at the moment. So I understand your desire to get into a position to get something out in November

recently = late 90s-ish

Here is a paper on a band gap using a voltage conveyer. https://www.researchgate.net/profile/Debashis_Dutta2/publication/4076556_A_programmable_CMOS_bandgap_voltage_reference_circuit_using_current_conveyor/links/0c960531969cf85ef1000000.pdf You can make a CCII- with 8 inverters. This will probably satisfy the requirement for a low voltage current conveyer described in the paper. To your other question there are indeed differential current conveyers. The DVCC is the classical one. You can make those with 10 inverters and they have been used for voltage references. I am a fan of inverter-based conveyers because you can skip all the transistor sizing issues by using a clkinv-sized standard cell. I wonder if it is possible to make a voltage reference entirely from standard cells?

thanks for the reference. It would be an interesting exploration to see if standard cells can be used for a reference. Could get a nice publication or two out of something like that.

Our team at MERL will be designing folded cascode that will be used for BGR and potentially for ADC as well. Waiting for spice models :)