https://open-source-silicon.dev logo
#analog-design
Title
# analog-design
t

Trevor Clarke

08/17/2020, 5:52 PM
has anyone been working on and opamp designs?
a

Adrian Freed

08/17/2020, 6:49 PM
@Trevor Clarke I have been looking at Current Conveyer designs using the standard cells.
t

Trevor Clarke

08/17/2020, 6:53 PM
I'm only somewhat familiar with CCs...If I understand correctly, different configurations of external components and they behave as various sources and amps? Are they differential? I'm looking to create a voltage reference and the standard implementation usually requires an opamp as a differential amp
y

yrrapt

08/17/2020, 7:01 PM
I'm not convinced you can get very far on the op-amp front without the spice models. Sure, you can draw up the schematics, maybe floorplan a layout but most of the design has to wait for the models
t

Trevor Clarke

08/17/2020, 7:24 PM
I agree you need to simulate, but starting with a design (including sizes) from another 130nm process is a reasonable starting point to get a bit further than just a floorplan
👍 1
y

yrrapt

08/17/2020, 7:26 PM
ignoring the differences between processes where would you get your hands on another 130 nm process?
Typically the first step in analogue design is characterising the process so that you know how to dimension your design
t

Trevor Clarke

08/17/2020, 7:30 PM
there are papers available for 130nm opamp designs....my assumption was that any 130nm process is likely to result in the right order of magnitude for sizes such that leaving somewhat generous gaps between elements would allow tuning of the sizes for the specific process...is this an off-base assumption?
y

yrrapt

08/17/2020, 7:37 PM
I guess it comes down to what performance you need/expect. Typically people would use the topology/design that's optimum for the task and that usually doesn't mean using "any old" design. But... having said all that, that's the "old" way of thinking which this community doesn't necessarily need to be limited to so maybe it's possible to get the performance required with a less rigorous approach. If it was me, I would leave a bit of time to come back and check all the biasing and stability at the very least once the models are available.
t

Trevor Clarke

08/17/2020, 7:41 PM
my understanding is that until somewhat recently lambda rules were often used to make designs somewhat process agnostic...they didn't make the most efficient designs so now it's more tailored to the process...since we don't have the characterizations yet I figured it might be reasonable to start with something more like that and get cells that do the job without meeting any particularly strict spec so there are some cells ready to test for november
and I do hope to check the biasing etc. when models are available but want to get something out as soon as possible....release early, release often
y

yrrapt

08/17/2020, 7:49 PM
I think that depend somewhat on your definition of how long ago 'recently' was... However, indeed I understand your approach. I've got a number of schematics setup just waiting for sizings (including an opamp). And working on layout setup at the moment. So I understand your desire to get into a position to get something out in November
👍 1
t

Trevor Clarke

08/17/2020, 7:50 PM
recently = late 90s-ish
a

Adrian Freed

08/18/2020, 12:19 AM
Here is a paper on a band gap using a voltage conveyer. https://www.researchgate.net/profile/Debashis_Dutta2/publication/4076556_A_programmable_CMOS_bandgap_voltage_reference_circuit_using_current_conveyor/links/0c960531969cf85ef1000000.pdf You can make a CCII- with 8 inverters. This will probably satisfy the requirement for a low voltage current conveyer described in the paper. To your other question there are indeed differential current conveyers. The DVCC is the classical one. You can make those with 10 inverters and they have been used for voltage references. I am a fan of inverter-based conveyers because you can skip all the transistor sizing issues by using a clkinv-sized standard cell. I wonder if it is possible to make a voltage reference entirely from standard cells?
👍 2
t

Trevor Clarke

08/18/2020, 1:57 PM
thanks for the reference. It would be an interesting exploration to see if standard cells can be used for a reference. Could get a nice publication or two out of something like that.
That BGR isn't likely to be small, multiple resistors and a DAC...but it's programmable which is nice. Worth having in the library for sure.
a

Affan Abbasi

09/02/2020, 4:33 AM
Our team at MERL will be designing folded cascode that will be used for BGR and potentially for ADC as well. Waiting for spice models :)
🤘 1