@User Can you elaborate on what you mean with synthesizable in your description ? You seem to add in transistors on VDD/GND of standard cells which in the terminology I am used to don't make them synthesizable.

Sorry for the confusion. That GND connection should say VSS - it’s detritus from from my microcap simulation.

Still I am not fully understanding what you actually imply with 'synthesizable'. In my terminology something is synthesizable if it can be described in RTL and mapped by the synthesis tool to standard cells.

I am using the term the way it is commonly used in the literature: what I described uses only digital standard cells. The connections can be described in verilog trivially. The part of the full synthesis chain which maps logic to a choice of cells is not useful in this case, the automatic placement and routing are. Clock synthesis not so much. Here is an example of how people talk about this and diagram it: https://fasoc.engin.umich.edu/