What kind of performance can you expect from this ...
# analog-design
What kind of performance can you expect from this technology? I made an inverter in spice and did an AC analysis, but I seem to be getting a few hundred MHz max. I set my supply to 1.8V and picked the LVT devices, and then played around a bit with M and W/L from the spreadsheet bins. (I seem to remember in uni we used W/L in the dozens with a bunch of fingers) And that's just an inverter... is it feasible at all to build a more complex circuit with a bandwidth of 500MHz?
@Pepijn de Vos Looking at your netlist transistor instances do not have dimensions. if no L and W are specified you get a W=1um / L=1um transistor which is of course extremely slow. Try to add these, using minimum nominal length (150nm i guess ) for the L ( so given the SCALE factor L=0.15 ) and may be W=1 for the Nmos and W=2 for the Pmos. Also your VCC supply is set at 5V, far above the max voltage for 1v8 transistors.
Thanks @Stefan Schippers @yrrapt @Adrian Freed! It was the end of the day and I was apparently going into completely the wrong direction. I was kinda assuming no W an L would be minimal sized, and was caught in a mental loop of more drive current -> increased width -> increased capacitance -> decreased size. I did also experiment with higher voltages, knowing it was invalid. That did improve speed slightly. I basically just graduated from my master IC design, so having a bit of a rough start with new everything and no guidance, but I'll manage hopefully. I'll read those paper and play around more later with a fresh brain.
No problem. I totally understand how easy it is to get caught in those loops. To put on my old man hat for a minute, its always worth starting from a paper calculation of the dominant pole in the system and then you'll see what you should expect and how to optimise by changing dc operating points (ie. W, L, Id, inversion coefficient) . That'll give you more intuition of where to make changes. It's so easy to get caught in a spice loop and in my experience that always leads to frustration
Yea I think that's a great approach, and one all my old-man teachers have been hammering on haha Even with sub-micron tech, they had us extract device parameters and do approximate calculations with a simple quadratic model. What do you generally use as a model for hand calculations? When I think of a mosfet paracitic capacitance I tend to think of the gate capacitance, but IIRC it's the drain-source capacitance that usually kills you, and tbh I'm a bit fuzzy on the physical cause of that one.