<@U018459959C>, <@U017UPJEGKZ>: The "harness" chi...
# analog-design
t
@User, @User: The "harness" chip (named "Caravel") will be provided to you and you will have a (I hope) more or less square area with access to pins on three sides and access to the wishbone bus of the picoRV32 processor that acts as "management" for the chip. All questions about the chip can be directed to either me or Mohamed Shalan, as the two architects of the system. The I/O pad cells are complicated things given to us by SkyWater. You will be able to use the management processor to configure various things like slew rate, drive strength, pull up/down, open-drain, etc., while you will have direct 3-pin access to each I/O pad as a digital bidirectional pad (in, out, and ~outenable). You can also shut down the digital part completely and connect directly to the pad as a direct analog signal. The verilog for the chip should be made available by the end of this week, and I hope to have a preliminary layout a week after that.
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b
Wow! Sounds like a monster! Will be very interesting to see :-)
r
@Tim Edwards @mshalan Has the harness chip (caravel) verilog been released. Also how about I/O pad cells release. What would be the notification process for the release? @ALI AHMED @Zain Khan
t
@Roomi Naqvi: I have the Caravel verilog essentially complete as of today. Because the verilog contains the I/O pads, I will not be able to release it until the I/O pads are released. However, Ahmed Ghazy, Tim Ansell, and I are hard at work preparing the I/O pad library for release. I would like to promise Monday, and I should have the Caravel RTL ready by then, but I'm not sure how long it will take to get the I/O pads up.
I might release the Caravel RTL anyway, although it would be unsimulatable without the I/O pads.
r
Yes please the Caravel RTL it would be helpful even without the I/O libs. @ALI AHMED @Hadir Khan
a
@Tim Edwards have u guys released Caravel RTL. If so , please if you can send me the link .
t
a
Thanks
@Tim Edwards Can we use mgmt side Peripherals like UART in our user area using wishbone and configure it thorough programming (UART register of mgmt core) ? Do we have access of mgmt core?
t
I suggest asking @mshalan . I think the processor only acts as bus master, but I am a bit vague on the operation of the crossbar switch.
a
Thanks @Tim Edwards, @mshalan your opinion on this?