@User, @User: The "harness" chip (named "Caravel") will be provided to you and you will have a (I hope) more or less square area with access to pins on three sides and access to the wishbone bus of the picoRV32 processor that acts as "management" for the chip. All questions about the chip can be directed to either me or Mohamed Shalan, as the two architects of the system. The I/O pad cells are complicated things given to us by SkyWater. You will be able to use the management processor to configure various things like slew rate, drive strength, pull up/down, open-drain, etc., while you will have direct 3-pin access to each I/O pad as a digital bidirectional pad (in, out, and ~outenable). You can also shut down the digital part completely and connect directly to the pad as a direct analog signal. The verilog for the chip should be made available by the end of this week, and I hope to have a preliminary layout a week after that.