@User: Nothing in this diagram should be taken as final. Also, the storage area is not currently in the existing RTL other than a memory map reference that is not connected to any wishbone bus. The 1k reference is currently mismatched to the OpenRAM verilog model in the code which is 8k words x 32 bits, but that refers to storage local to the management SoC. The storage area shown above is supposed to be a 32k x 32 bit memory accessible to the user project area. The status of that storage area for the first shuttle run is heavily dependent on the status of OpenRAM.