Trevor Clarke

11/12/2020, 7:01 PM
how do I include a finalized analog cell in the verilog when integrating to caravel? this might be an #openlane question more than here..


11/12/2020, 7:44 PM
I don't think you have to integrate into verilog/openlane unless you want to. I'm not sure if you want to or not

Tim Edwards

11/12/2020, 7:52 PM
@Trevor Clarke: It's best to add it to the verilog as a "black box" entry so that it can be used for LVS. That is how I have been doing full-chip LVS, comparing the layout-extracted netlist to the top level verilog. For that, I just generate a behavioral verilog model for the analog block; if you don't feel the need to simulate the functional behavior of the block in verilog, then it can be empty. See, for example, my power-on-reset block in caravel. That is not synthesized, but is a block with analog components, with a very lightweight behavioral model, and it will pass LVS.
@Trevor Clarke: Make sure that port names in the verilog module match the port names in the layout.
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