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#analog-design
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# analog-design
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Tim Edwards

11/22/2020, 3:50 AM
@User: The devices I referred to are in sky130_fd_pr and are called "rf_test_coil1" through "rf_test_coil3". They have a weird pizza-slice pattern drawn on top in the LVS text layer which I don't know the reason for. Otherwise, they look like typical octagonal coils. Probably it would be best to give up on those, and make a parameterized cell that automatically generates coil designs, then fill a test chip with them, and figure out how to map the coil parameters to the measured inductance.
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Affan Abbasi

11/22/2020, 4:30 AM
Thank you for the reply. I don't think there is enough time for me to start/finish a PCELL. However, I can do a manual layout for square spiral inductor by using online calculator(http://smirc.stanford.edu/spiralcalc.html). So should I use metal5 for that or redistribution layer? Why there will be bump bonds on whole layout? For flip chip?
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Tim Edwards

11/22/2020, 2:46 PM
@Affan Abbasi: There will be no opportunity to do anything on the redistribution layer other than the bump bonds for this shuttle run. After some suggested changes by SkyWater, there is now more area on the chip and I would like to redesign the bump pattern with space in the middle for inductor experiments. But that requires some significant redesign and will have to wait for another shuttle run. The existing bump bond pattern will cover the surface with a 6x10 array at a 500um pitch. Meanwhile, the metal5 layer is pretty thick and should give you some decent inductors; while not as thick as the redistribution layer, I assume it is much better controlled.
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diadatp

11/22/2020, 5:51 PM
@Affan Abbasi Have a look at https://github.com/patrickschulz/openPCells. It's a PCell generator that's set up for SKY130. It has a square and octagonal spiral inductor generators.
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Here is a script to iterate through the design space for an asymmetrical square m5 inductor using FastHenry. https://github.com/diadatp/sky130_rf_tools/blob/main/fasthenry/iterate_fh.py It matches the formulae from the page you shared quite well.
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@Tim Edwards By test chip, do you mean one of the 41 user slots or the 42nd one? I have made test structures for an inductor along with de embedding for use with GSG probes. Is this something that could make it onto the 42nd die area?
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Affan Abbasi

11/22/2020, 6:00 PM
@diadatp Many thanks.
@Tim Edwards @diadatp Can I have similar test structures with pads in the center of the core area?
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diadatp

11/22/2020, 6:03 PM
I considered putting similar structures on a user die but the RDL routing above and requirement that every de-embedding structure and DUT "seeing" the same environment around it makes that route seem unlikely.
@Affan Abbasi This might be relevant to your question: https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1603891703159400
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Affan Abbasi

11/22/2020, 6:12 PM
@diadatp Hmmmm......so I can have probe cuts in the center and can remove bonds from 100 or 50 samples that I'll receive after tapeout? I have the capability to do my own wirebonding.
@diadatp @Tim Edwards do we have information about top metal, is it copper or Aluminum? I can easily do wirebonds on Aluminum but copper is not going to be fun because of oxidation.
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Tim Edwards

11/22/2020, 8:34 PM
@Affan Abbasi: Top metal of the SkyWater part of the process (metal 5) is aluminum. The redistribution layer (post-processed by a 3rd party supplier) is copper.
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Affan Abbasi

11/22/2020, 8:35 PM
@Tim Edwards Thank You
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Tim Edwards

11/22/2020, 8:42 PM
@diadatp: SkyWater reserves the 42nd spot for their own uses. We agreed on 40 slots, so the 41st is technically an "extra". I could envision using the space for experiments in the redistribution layer (either added or subtracted). The only real restriction is that the padframe has to be the same size as Caravel, because of the space reserved in the reticle frame (the easiest thing to do there would be to use Caravel, but wirebond it). The more important part would be convincing @Tim 'mithro' Ansell that we should have one slot for an "almost anything goes" purpose, as there is simplicity (read: low budget) in having every single die treated exactly the same. But it's easy enough to generate a pick map for the wafer.
@Affan Abbasi: The plan on record is that all chips are covered with an array of bump bonds. Those that are assembled on boards are done flip-chip style. We will only give you a limited number (one?) of assembled boards, but you will get plenty of additional unassembled parts back as well. What you do with those is up to you. If we do allow for a chip without bump bonds, we aren't going to be sending it to a packaging house, so you'll just get back bare parts. Note that this is all speculative unless agreed to by all parties.