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Tim Edwards

11/27/2020, 3:41 AM
@User: There is no example of a project using analog. However, the general rule is: Connect to any GPIO pad above GPIO[7] (the ones from 0 to 7 will be connected to other chips on the development board). Connect to the pins in the user project wrapper cell called "analog_io". The management SoC must then execute a program on startup that turns off all digital signals on the GPIOs where you are using analog signals. There is one "analog_io" signal per GPIO pin. Bear in mind that the analog_io pin connects directly to the pad (through a small resistor).
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Roomi Naqvi

11/27/2020, 4:35 AM
@Arsalan Athar @Affan Abbasi @ibad1112
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Tore Leikanger

11/27/2020, 7:38 AM
@Juha Häkkinen
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Diego Hernando

11/27/2020, 3:24 PM
Thanks for your replay @Tim Edwards !
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Pepijn de Vos

11/27/2020, 4:21 PM
But will this allow more than 1.8v? I assume the digital stuff that controls the pin runs at that level, and would be a shame if some 20v analog designs blows up because of that.
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Tim Edwards

11/27/2020, 4:38 PM
@Pepijn de Vos: The pads may be driven up to 5.5V, although anything above 3.3V requires the 3.3V voltage regulator on the demonstration/development board to be replaced.
The digital signals to the pad are 1.8V, but everything is level shifted up internally to the VDDA (3.3V) domain.
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Pepijn de Vos

11/27/2020, 4:42 PM
Alright. I was planning to use the 10v5 devices with +5 and -5v, but I can scale back my plans a bit. (not for this shuttle run anyway)
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yrrapt

11/27/2020, 5:07 PM
@Tim Edwards has the final user area gds been released yet or still working through the 40 -> 41 change? Looking at the repo
user_project_wrapper_empty.gds
was last updated 8 days ago so I guess not but just want to double check
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Tim Edwards

11/27/2020, 7:06 PM
@yrrapt: Final GDS is supposed to be ready today, as I understand it.
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yrrapt

11/27/2020, 7:06 PM
@Tim Edwards Great, thanks for the update
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ibad1112

11/30/2020, 11:20 PM
@Affan Abbasi This answer tells to connect to the analog io pins in layout
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