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<@U016H5X1K62> Also if you don't mind can you send...
# analog-design
i
ibad1112
11/30/2020, 11:00 PM
@User
Also if you don't mind can you send me your user project wrapper.v and top layout file just so that I can see how connections are done in verilog.
ibad1112
11/30/2020, 11:07 PM
@Tim Edwards
ibad1112
11/30/2020, 11:08 PM
sorry wrong tag, the heats getting to my mind
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