I realized that the sky130 pdk has a deep N well for isolating nfets. Has anyone done anything with this? I searched the channel but did not see any talk about it.
04/17/2021, 10:51 PM
In general or for this particular PDK? I've used deep NWells in other processes
04/17/2021, 10:53 PM
Both I guess. General in that because it exists, is there any reason not to use it for all the analog nmos and specifically to the pdk in terms of it it changes anything.
04/17/2021, 10:57 PM
I've used it when I needed to isolate the FET to design say a charge pump. If I remember correctly, for other PDKs there have been restrictions on a) how large the deep-nwell layer can be, and b) the voltages that you'd need. I do remember finding it a pain to deal with in some of the lower technology nodes, so that might explain why we didn't just spam it everywhere.
I assume for power-designs you'd want to use it in strategic places. I can't give you more input on this particular one.
04/18/2021, 1:01 AM
The main issue (for me, anyway) right now with deep N-well is that magic will not correctly extract the isolated P-well structure in it. I spent a week on coding that into magic but only got it partly working, so I haven't pushed that update yet. So structures in deep N-well tend to fail LVS. But if you're doing analog circuits and need noise isolation, then you should use it. I'll get the extraction working sooner or later.
04/18/2021, 8:45 AM
@Weston Braun I used it for the bandgap for noise isolation on my submission on mpw-a. Took a little bit of trial and error to work out the correct spacings for DRC.
I recommend having a look at my submitted GDS and copying the spacing as the fastest way to get up and running
Luis Henrique Rodovalho
04/18/2021, 2:33 PM
Does isolated NMOS devices have their own cellviews and models for the Cadence Skywater PDK? I'm used to isolated NMOS in other PDKs, and the models are almost the same, but they have different extracted names, such as nmos2v_dnw (deep n-well), for TSMC 018.